# Two-Stage Common Emitter Amplifier Is Clipping Unexpectedly

I've been reading about multistage common emitter/source amplifiers and have decided to test some high-gain designs with PSPICE. One design has me very confused and I was wondering if someone could explain its behavior. I have a green voltage probe on the first stage and a red voltage probe on the second stage. Both stages are identical and are AC coupled. Why does the PSPICE simulation result in the following output waveforms? The final output clips at 5V and 15V as expected, but I'm unable to explain the behavior of the first stage. Thanks!

• Reduce your input signal. The gain around Q6 is pretty high.
– JRE
Jun 26, 2017 at 5:23
• Take a look at your DC-bias for each stage. Jun 26, 2017 at 6:14
• you appear to be doing nothing to control the AC gain of this circuit. add some un-bypassed resistance on the emitters. Jun 26, 2017 at 6:16

I'm unable to explain the behavior of the first stage

• Single resistor biasing of a base like you have done is never very precise and relies on the hFE of the transistor for setting the quiescent DC operating point (bad). Use a potential divider bias with lower values like tens of kohm.
• Relying on emitter resistor bypass capacitors for increasing gain inevitably introduces bad distortion. Do you see this technique ever used in any op-amp?

Result is drift and distortion.

It looks as though you tweaked $R_{56}$, for example, in order to get a collector voltage on $Q_6$ that was exactly half-way between your rails. I'm just guessing, but that's what it looks like to me.

Aside from the comments Andy made (all good), your $I_Q\approx 5\:\textrm{mA}$ in the first stage and voltage gain is going to be somewhere between 200 and 300, at a guess. Probably close to 250. So this would predict about $\pm 25\:\textrm{V}$ swing at the collector of $Q_6$, which you already know can't happen. What's going to happen instead, once of course equilibrium in your circuit is reached, is that $Q_6$, which only has a quiescent $2.5\:\textrm{V}$ across its emitter/collector leads, is going to go between saturation and active modes. Not so good in most circumstances (though perhaps you want that -- who knows?)

Trying to understand the green curve that is showing is pretty much completely unimportant. It does not represent reality, as I'll now discuss.

Spice behavior follows these steps:

1. Do a DC operating point step to establish the starting operating points.
2. Initially set up capacitor voltages as if a .ic card had been provided that magically set up the capacitor voltage values perfectly to the computed DC operating point arrangements (which ignored them.)
3. Start the run.

Since your $Q_6$ BJT isn't saturated during the DC operating point step (#1 above), Spice will calculate all the right values to get started on that basis. But Spice will soon discover, once it starts the run and "observes" the saturating behavior, that the DC operating point capacitor voltage values it had computed earlier are pretty much worthless now that it is running around computing changes.

This means that the initial period here, shown by your green curve, is effectively worthless because the initial computation by Spice didn't hit the mark and it is now spending simulation time trying to re-establish a new equilibrium. The curve you see is that process unfolding and you cannot assume it is very meaningful. You won't see it in a real circuit because real circuits don't do a "DC operating point" computation!! So it's not going to be very useful to you.

If you want to get something closer to reality, you could tell Spice to skip the DC operating point calculation step ("UIC" on the .tran card.) Then the capacitors will start up without any voltage across them, which is often the case when you power up a circuit. Then you'll see just how long it takes to charge things up. Try a run for 10 seconds and see.

If you then take a look at $V_{CE}$, near the end of the 10 second run, I think you'll see that it gets very close to $0\:\textrm{V}$ because the BJT is pinched into saturation. This saturation effect establishes a different operating point and it takes Spice a while to find it. And the collector voltage curve will now look different than what you show.

Let's make the first stage a little better (still, not one I'd ever actually use, as bootstrapping is just too good to pass up in practice) and a little less dependent on the $\beta$ and $I_{SAT}$ of the BJT. We need specs:

• Enough gain to make good use of the $+15\:\textrm{V}$ rail.
• Reasonable linearity.
• Reasonable temperature stability.

Start by setting the quiescent collector current and emitter and collector voltages. From the datasheet I see that they use $2\:\textrm{mA}$ to provide a stated current gain. So that might be a starting point. The current gain curve seems to flatten off around $10\:\textrm{mA}$ and you were using $5\:\textrm{mA}$. All this tells me that I can keep your figure. So $I_Q=5\:\textrm{mA}$. Next, with as much headroom as you have here, I like to get the DC operating point of the emitter at $2\:\textrm{V}$ to for thermal stability of the gain. So $V_{E_Q}=2\:\textrm{V}$. I also like to set the minimum $V_{CE}=4\:\textrm{V}$ -- the datasheet suggests more, but not a lot more. Less is okay if tight for voltage. But you aren't. So this leaves me about $9\:\textrm{V}$ of total swing at the collector. Half of that is $4.5\:\textrm{V}$, so this means $V_{C_Q}=2\:\textrm{V}+4\:\textrm{V}+4.5\:\textrm{V}=10.5\:\textrm{V}$.

Now, ignoring $\beta$, I can compute standard values for the emitter and collector resistors as $R_4=\frac{2\:\textrm{V}}{5\:\textrm{mA}}\approx 390\:\Omega$ and $R_5=\frac{15\:\textrm{V}-10.5\:\textrm{V}}{5\:\textrm{mA}}\approx 910\:\Omega$.

Estimating $V_{BE}=700\:\textrm{mV}$, I then get $V_{B_Q}=2.7\:\textrm{V}$. This is the target I'd like to hit. A resistor divider can do this. Given the high current gain of the BC549C, the base current is likely to be close to $10\:\mu\textrm{A}$. But given variability, I'd go with twice that as an estimate. The "stiffness" of the resistor divider should be such that it can easily provide that base current without a large shift in the divider voltage. So let's use $400\:\mu\textrm{A}$. This means $R_1=\frac{15\:\textrm{V}-2.7\:\textrm{V}}{400\:\mu\textrm{A}}\approx 33\:\textrm{k}\Omega$ and $R_2=\frac{2.7\:\textrm{V}}{400\:\mu\textrm{A}-20\:\mu\textrm{A}}\approx 7.5\:\textrm{k}\Omega$. (Note that the input impedance of this new design is now a lot lower than your case.)

Now, given we only have room for a gain of at most $\frac{4.5\:\textrm{V}}{100\:\textrm{mV}}=45$, let's select a gain of $35$ as a rough target. This means that $R_5=\frac{R_3}{35}\approx 27\:\Omega$:

simulate this circuit – Schematic created using CircuitLab

The actual gain will be a noticeable bit less, though. This is because of your very low frequency and the capacitor values, as well as $r_e\approx 5\:\Omega$. Your $100\:\mu\textrm{F}$ emitter bypass capacitor exhibits about $X_C\approx 27\:\Omega$ and your $10\:\mu\textrm{F}$ DC blocking capacitors exhibit about ten times that or $X_C\approx 270\:\Omega$. Now, these have to be added as vectors, so they don't directly add. But in the emitter leg, since $R_5=27\:\Omega$ and since $X_{C_1}\approx 27\:\Omega$, these will result in about $45^\circ$. So, all put together I get a gain at $60\:\textrm{Hz}$ of about 23 and not 35 (discounting the minor loss due to $X_{C_2}$ and its loading before the BJT sees the signal.) So I'd expect a peak-to-peak collector signal of about $V_{PP}\approx 4.5\:\textrm{V}$. (This would increase if you increased the frequency you were applying -- given the existing capacitor sizing and gain and operating point, your design is frequency-dependent especially at these lower frequencies.)

But at least, now, you have reasonable linearity, a relative lack of dependence of the operating point on $\beta$ and $I_{SAT}$, and some stability against temperature changes as the circuit warms up or experiences ambient temperature changes.