There are at least 2 issues here: thermal surges, and VDD transients.
Lets put some numbers on this. Assume transistors with silicon-extent of 20 micron by 20 micron, and 10 micron depth. The volume thus is 20*20*10, or 4,000 cubic microns. Older technology bipolars, with collectors under the base-emitter region, are approximately this size. The specific-heat of silicon is 1.6 picoJoules/cubicmicron/°C. Our device is 4,000 * 1.6pJ = 6.4 nanoJoules/°C. How much temperature rise can we generate, in 10 nanoseconds of thermal spike?
Use 5 volts, and use 100 milliAmps (a rather good spike, between 2 opposing bus driver transistors). The power is 0.5 watts, and energy is 0.5 nanoJoules per nanosecond. In 10 nanoseconds, the energy is 5 nanoJoules.
Now just divide: 5nJ / 6.4nJ == 0.8°C rise. Assumed uniformly distributed inside the 20*20*10U volume. Given the majority of bipolar volume is the buried collector, "uniform" is valid assumption. Thus 1°C is answer, per buss driver. If 8 drivers are in one package, does the 1°C number change? No, because the heat sources are spread around in 8 different regions, and the transient occurrence is low duty cycle.
Now for that second issue: the VDD ringing. Early buss driver ICs held 8 circuits, with only one GND and one VDD. Rail collapse was a big problem. Why?
Assume 10nS GND+VDD inductance. Assume charging 8 loads, 50pF each, with Trise of 10ns. Or 2 volts/nanosecond slewrate.
Given 1pF at 1v/ns needs 1mA, our single output needs 100mA. The eight outputs need 800 mA. Assume the charging surges rises from ZERO current to 800mA, in half the time, or 5ns. What is the rail bounce?
V = L * dI/dT = 10nH * 0.8amp/5ns = 1.6 volts. Thus GND moves up by 0.8v and VDD moves down by 0.8v.
Because I assumed a triangular current pulse (rising and falling in 5ns), the charging rate is less than needed. To meet the full-charge pulse timing, we need to double the peak currents, and the bouncing becomes 1.6 volts for both GND and for VDD.