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I'm working on a home-brew CPU design, with the usual mix of parallel EEPROMs, static RAMs and registers, tri-stated onto a single 8 bit bus.

My /output-enable logic for three tristate-able chips on the databus is:

/Ken = /a
/Ren = /a nor /b
/Men = /a nor (/b nor /b)

Do I need to worry about the few nano-seconds during which more than one chip's /oe pin will be low, due to the differing number of gates?

Will current flowing out of a high output of one chip, into a low output of another chip, for less than 10ns cause damage?

If it would cause damage, how was this situation avoided in the 1970's-80's?

Update: Chips are:

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There are a number of ways to create nonoverlapping enables for bus devices. Perhaps the simplest is to add the clock signal itself to your equations. Then, only one device at a time is enabled while the clock is high, and no devices at all are enabled while it is low. (Or vice-versa if you're using the rising edge of the clock to capture data.)

Normally, the output-enable function of most devices is fast enough that "wasting" half of each cycle in this way does not cause a timing problem. But if it does, one workaround is to modify the duty cycle of the clock as needed.

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  • \$\begingroup\$ Your answer implies that enables which overlap by a few nanoseconds will cause damage. Have I read this correctly? \$\endgroup\$ – fadedbee Jun 26 '17 at 12:09
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    \$\begingroup\$ No, I'm not saying that there will definitely be physical damage, but since the situation is rather easy to avoid in the first place, why put the extra stress on the components? \$\endgroup\$ – Dave Tweed Jun 26 '17 at 12:13
  • \$\begingroup\$ Thanks for clarifying that. I am trying to keep the number of chips under control/ I could AND each of the enable signals with a clock, but that will be another chip and yet more breadboard wires. \$\endgroup\$ – fadedbee Jun 26 '17 at 12:16
  • \$\begingroup\$ You already have a common signal /a going to all three output enables -- just combine the clock with that. In the '80s, this kind of decoding would have been done in a PAL, so there would be no incremental cost for adding another signal to each equation. \$\endgroup\$ – Dave Tweed Jun 26 '17 at 12:23
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    \$\begingroup\$ In the '70s, a dedicated decoder chip would have been used (e.g., 74138/139). These generally have plenty of extra enable inputs, one of which would be used for this purpose. \$\endgroup\$ – Dave Tweed Jun 26 '17 at 12:34
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Typically the situation was avoided by the outputs being open-collector instead of tristate, with a pullup resistor to +5V completing the circuit. If one device drove the shared line low and the other went open-collector, the shared line would stay low. If there was only a conflict for a very short time, this would cause no problems at all.

For a practical example of this, the CAN bus is widely used in industry (particularly in cars) and operates in exactly this way. Every device's output is open-collector with a current limit, and one device (and one only) contains the pullup resistor. In an industrial/automotive context where devices can and do go wrong, and wires can also be shorted high or low, this ensures that no device's output can damage another device, however it goes wrong. In addition, the CAN bus driver for each device monitors the bus to check that it goes to the expected state, and reports bus errors to the application if it finds a conflict where someone else is stomping over its data.

In practise this is unlikely to damage the chips. However it will give instantaneous current spikes on outputs where high and low are shorted, which does unpleasant things to EMC emissions. Designers in the 70s and 80s were much less concerned about EMC, so it's likely that many circuits went out of the door with exactly this problem.

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  • \$\begingroup\$ Just a follow up: CAN buses often have a terminating resistor to prevent reflections. This is usually more important on longer wires, but might be important to consider for buses that operate at HF+ frequencies. \$\endgroup\$ – Tyzoid Jun 26 '17 at 16:58
  • \$\begingroup\$ Data bus outputs weren't usually open-collector, but low-side drivers on NMOS devices were much stronger than high-side drivers. This was offset by the fact that the switching voltage was closer to the negative rail than to the positive rail. \$\endgroup\$ – supercat Jun 26 '17 at 16:59
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If it would cause damage, how was this situation avoided in the 1970's-80's?

manual design that compensated the delay.

Whether this will cause damage depends on your technology, so no general advice can be given; however, for a transient of 10ns to have effect, your system needs to have a bandwidth > 100MHz, so that's something you can actively avoid.

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  • \$\begingroup\$ There will be a 1MHz clock and it uses 74HCxxx logic at 5v. Nothing will latch the value of the bus during these few ns. My concern is not the existence of a transient, but whether a transient will destroy chips by allowing current to flow. \$\endgroup\$ – fadedbee Jun 26 '17 at 11:19
  • \$\begingroup\$ Maybe you could limit the current with a small resistor? \$\endgroup\$ – Dampmaskin Jun 26 '17 at 11:20
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If a device is designed to output data as quickly and strongly as possible when /OE is asserted, bus contention could result in substantial peak currents which may cause unwanted noise on the supply rails even if they don't cause physical damage. On the other hand, such a device may be able to drive the bus to a valid state in less than half a clock cycle, in which case gating /OE with the clock may avoid such contention. Some other devices, however, can't drive the bus so quickly and would need to have closer to a full cycle to drive the bus. Devices which drive the bus more slowly, however, are less apt to pass excessive current during momentary periods of device contention.

A couple-nanosecond difference in when devices receive enable signals isn't apt to matter as much as the timing with which the devices themselves respond to enable signals. If a device is slow to release the data bus, it may be necessary to control its gating signal so that it gets released early to ensure that by the time another device tries to drive the bus the first device will have ceased driving it.

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There are at least 2 issues here: thermal surges, and VDD transients.

Lets put some numbers on this. Assume transistors with silicon-extent of 20 micron by 20 micron, and 10 micron depth. The volume thus is 20*20*10, or 4,000 cubic microns. Older technology bipolars, with collectors under the base-emitter region, are approximately this size. The specific-heat of silicon is 1.6 picoJoules/cubicmicron/°C. Our device is 4,000 * 1.6pJ = 6.4 nanoJoules/°C. How much temperature rise can we generate, in 10 nanoseconds of thermal spike?

Use 5 volts, and use 100 milliAmps (a rather good spike, between 2 opposing bus driver transistors). The power is 0.5 watts, and energy is 0.5 nanoJoules per nanosecond. In 10 nanoseconds, the energy is 5 nanoJoules.

Now just divide: 5nJ / 6.4nJ == 0.8°C rise. Assumed uniformly distributed inside the 20*20*10U volume. Given the majority of bipolar volume is the buried collector, "uniform" is valid assumption. Thus 1°C is answer, per buss driver. If 8 drivers are in one package, does the 1°C number change? No, because the heat sources are spread around in 8 different regions, and the transient occurrence is low duty cycle.

Now for that second issue: the VDD ringing. Early buss driver ICs held 8 circuits, with only one GND and one VDD. Rail collapse was a big problem. Why?

Assume 10nS GND+VDD inductance. Assume charging 8 loads, 50pF each, with Trise of 10ns. Or 2 volts/nanosecond slewrate.

Given 1pF at 1v/ns needs 1mA, our single output needs 100mA. The eight outputs need 800 mA. Assume the charging surges rises from ZERO current to 800mA, in half the time, or 5ns. What is the rail bounce?

V = L * dI/dT = 10nH * 0.8amp/5ns = 1.6 volts. Thus GND moves up by 0.8v and VDD moves down by 0.8v.

Because I assumed a triangular current pulse (rising and falling in 5ns), the charging rate is less than needed. To meet the full-charge pulse timing, we need to double the peak currents, and the bouncing becomes 1.6 volts for both GND and for VDD.

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