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I am creating a precision 3A current sink which functions when connected to 12+ volts. I am using the following circuit:

The voltage reference is created by a 0.4V precision reference chip (LT6650CS5) and divided down to 0.3V.

For some reason the output of my Op-Amp is oscillating instead of settling which is causing the output of the FET to oscillate.

Op-Amp output (vout1) Op-Amp output (vout1)

Any ideas?

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    \$\begingroup\$ Add a small capacitor(~100pF range) right between your output and negative opamp input. Go further, connect resistor in kOhm range between vfb1 and negative terminal so that capacitor has some impedance to work against \$\endgroup\$
    – Bip
    Commented Jun 26, 2017 at 19:02
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    \$\begingroup\$ I'm not real good at this, but I think the gate capacitance is too high for the opamp. The gate capacitance (if I'm reading the datasheet correctly) is 1600 pF. The opamp datasheet says the maximum capactitive load is 1nF (1000pF.). That coukd be enough to make the opamp unstable. \$\endgroup\$
    – JRE
    Commented Jun 26, 2017 at 19:08

2 Answers 2

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Do this to isolate the heavy load of the gate from the AC feedback path of the op-amp. The DC feedback path remains accurate.

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ The missing bit: MOSFET gate is a capacitor Cgs. Load at the opamp's output is Cgs in series wien R3, but R3 is too small to matter. Problem with capacitive loads is they add a phase shift in the feedback loop, which reduces phase margin and means Nyquist's criterion for stability will not be met, and the opamp will oscillate. Spehro's circuit decouples the opamps' feedback loop from the capacitive load and thus makes the opamp stable. \$\endgroup\$
    – bobflux
    Commented Jun 26, 2017 at 21:36
  • \$\begingroup\$ Note that the approach in the answer is needed when the load resistance is low. For low-current sources with loads in the kOhms and more, the Cgs does the job of stabilizing the op-amp, and no series resistors are needed :) \$\endgroup\$ Commented Feb 21, 2022 at 5:08
  • \$\begingroup\$ @Kubahasn'tforgottenMonica The critical number is the ratio of the sense resistor R3 to the op-amp output resistance R0 (maybe 100 ohms for a general-purpose op-amp to 1K ohm for a micro power op-amp) to. In the above example it is <<1. If the ratio is >> 1 then the phase margin will hardly be affected. The lower it is the better the chances there is a frequency that will support oscillation (or cause over/undershoot). So a low-current sink that has a very low sense resistor (say 1 ohm with 50uV across it = 50uA) using a low Vis op-amp could well oscillate. \$\endgroup\$ Commented Feb 21, 2022 at 6:17
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You will have to add a small series resistance to the output of the op amp and a small feedback cap to allow the op amp to drive the capacitive load of the MOSFET gate.

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    \$\begingroup\$ You were downvoted (not by me) because you were fundamentally wrong. The desired loop gain is 1, which the direct feedback provides, and the desired error is very small - again the direct feedback produces it. The comments and Spehro's answer provide the proper approach. \$\endgroup\$ Commented Jun 26, 2017 at 21:23

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