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I was solving the exercise problem 4.17.6 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition):

Percentage occurrences of the instructions are as follows: enter image description here and following are the clock cycles sizes for different stages: enter image description here We can convert all load/store instructions into register-based (no offset) and put the memory access in parallel with the ALU. Assume that the latency of the new EX/MEM stage is equal to the longer of their latencies. This change requires many existing LW/SW instructions to be converted into two-instruction sequences. If this is needed for 50% of these instructions, what is the overall speedup achieved by changing from the 5-stage pipeline to the 4-stage pipeline where EX and MEM are done in parallel?

The solution given is as follows:

The latency of the pipelined datapath is unchanged (the maximum stage latency does not change). The clock cycle time of the single-cycle datapath is the sum of logic latencies for the four stages (IF, ID, WB, and the combined EX + MEM stage). We have: enter image description here The number of instructions increases for the 4-stage pipeline, so the speedup is below 1 (there is a slowdown): enter image description here

Doubt
I feel this is pretty wrong. The solution simply seeks to first find the increase in the number of instructions and then compare them. $$\frac{1}{1.15}=0.87$$However it neglects the increased clock cycles (from 200ps to 215ps) and decreased stage count (from 5 to 4). I feel it should be $$\frac{5\times 200}{4\times 215\times 1.15}=1.01$$ So there is indeed little speedup. Am I right?

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  • \$\begingroup\$ They are comparing two pipelines, why do you thing the stage latency is modified between them? What would be the interest of a pipeline if you had to take into account the number of stages as you are doing? \$\endgroup\$ – AProgrammer Jun 28 '17 at 9:06
  • \$\begingroup\$ ok it seems that I made mistake and latency in both examples (a) and (b) is 215ps in both cases 5 stage and 4 stage pipeline, so we can ignore it, right? I don't feel it right to compare two pipelines if they don't have implicit matching parameters (here number of stages and cycle time), because both of them affect the actual execution time. \$\endgroup\$ – Maha Jun 28 '17 at 15:22
  • \$\begingroup\$ Why would the number of stages affect the actual execution time? (Assuming there is no stalls) \$\endgroup\$ – AProgrammer Jun 28 '17 at 15:27
  • \$\begingroup\$ Ohhhh I guess I was making mistake by considering time required to execute one instruction against instead of considering instruction throughput which stays steady as long as cycle time does not change... Am I right? \$\endgroup\$ – Maha Jun 28 '17 at 17:36
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    \$\begingroup\$ Yes on both point. \$\endgroup\$ – AProgrammer Jun 30 '17 at 6:28

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