# Should I optimize ground plane for AC or DC return currents?

I am doing a 2 layer PCB. Based on my resaerch I have solid ground plane on the bottom and try to route as much as possible on top with unavoidable crossings on the bottom. (see here and here). But you can have at least 2 ways implement such crossing (horizontal and vertical) and the question is about the best way to roganize them.

I explain further based on my example:

I have digital connector on top (designed to be plugged directly to a part of I/O of Raspberry Pi). Therefore I preferred vertical crossings, because they present smaller obstacle for the DC currents flowing toward ground pin on the top connector (yellow line).But then I remembered that AC currents (light blue) try to follow the corresponding trace on top, and got doubts if got it right. The question in other words, should I keep current implemention or scrap it and try to minimize the paths of AC return currents?

The AC in this case is represented by SPI interface, which despite being nominally relatively low frequency, would still produce high frequencies on level transitions (edges)

EDIT: while giving it a thought I decided to move the IC on the top right to the left and here is the result: I beleive, this improved the layout (i. e. eliminated the cluster of crossings) to the point making the question irrelevant for this example. But since this sis perhaps not my last engineereing task, I still would like to get the anwser.

• Calculate ESR and ESL. Compute for jw (omega). Boom! You have your impedance. There is no "current takes path of least resistance" AC and DC currents divide according to KCL for the different paths' impedances and their respective frequency. Jun 28, 2017 at 15:03
• Being serious about the layout is very important. But sometimes you should just let go. Your layout seems quite simple, so just do it carefully, most probably you would never see a difference.
– user76844
Jun 28, 2017 at 17:01
• updated the post Jun 28, 2017 at 20:19
• How LOW should the analog noise be? What Effective Number Of Bits do you wish, for what fullscale ADC input? Jun 29, 2017 at 3:46

Below 100KHz, currents explore all possible paths, proportional to conductance (actually its called susceptance for AC); consider some path that is 4" long; how does that path inductance compare to resistance of the copper foil (assume 1mm wide path).

The reactance of 100nH (4" wire) at 100KHz is = (2*pi*1e+5)*1e-7 = 0.0628 ohms. What is the path resistance (4" or 100mm by 1mm) with 100 squares of copper, at 500 microOhms per square? R = 50 milliOhms or 0.050 ohms.

Thus at 100KHz, the inductance of 4" path is approximately same as the resistance. The inductance is beginning to affect how the currents explore all possible RETURN paths.

Your SPI edges will be much faster than 100KHz, unless you slow them.

• updated the post Jun 28, 2017 at 20:19

At the relatively moderate frequencies used in SPI, and absent any requirements for very low noise, your design is probably sufficient. I would focus on minimizing the number of breaks in the ground plane, and when there are breaks keeping them as short as possible. Looks like you've already done that much.

If you need very low analog noise, you'll additionally want to isolate the digital and analog portions of the board. Often this manifests as an isolated ground pour for the analog section, connected to the digital section at exactly one point. In this way, no digital return current can ever use any part of the analog ground plane. Research "single point ground" and "star ground". Searching for "ADC ground layout" and similar will also turn up dozens of application notes with ample detail.

When designing such circuits, I tend to use two distinct ground symbols and nets (say DGND and AGND), and connect them with a 0 Ohm resistor. It makes it easier to prevent accidentally connecting them when doing the PCB layout, and it ends up being a convenient test point on the prototype board. Assuring external connections don't undermine the design is usually the trickier part.

• There is a requirement for low analog noise. Jun 28, 2017 at 20:02
• updated the post Jun 28, 2017 at 20:19