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Can somebody tell me how can the data be read before the address is even loaded. In the image, the data is read before the address was completely loaded. enter image description here

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  • \$\begingroup\$ What? I see the data is loaded on the \$T_3\$ period, while the address is on the bus since \$T_1\$.. \$\endgroup\$ – Eugene Sh. Jun 28 '17 at 21:29
  • \$\begingroup\$ Yes but the addres has not finished loading. Data begins before the address is finished. \$\endgroup\$ – Fare Osoba Jun 28 '17 at 21:32
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    \$\begingroup\$ What do you mean by "completely loaded"? The address is valid on the bus for a long time (\$T_{AD}\$ after the first rising edge), which gives the memory (or whatever) plenty of time to retrieve the correct data. \$\endgroup\$ – Dave Tweed Jun 28 '17 at 21:32
  • \$\begingroup\$ Then how long does it take for the bus to access the address? Is it less than 1 clock cycle? \$\endgroup\$ – Fare Osoba Jun 28 '17 at 21:39
  • \$\begingroup\$ You're using standard words in nonstandard ways, which is only confusing matters. Remember, the "bus" is just a set of wires that connects a CPU to a memory. The bus doesn't "access" anything, it just transfers the address to the memory and then transfers the data back to the CPU. The diagram is simply showing the timing relationships between these events. \$\endgroup\$ – Dave Tweed Jun 28 '17 at 21:47
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This diagram is drawn from the perspective of the CPU, accessing 'an external memory'. It is a description of what it will supply the memory with, so that you can design a memory that meets the CPU's timing requirements.

The CPU guarantees to have set the address lines to a VALID address, that is, the address lines will have stopped changing, by \$T_{AD}\$ after the start of the \$T_1\$, and to keep it stable until the read has finished.

It will set \$\overline {MREQ}\$ active, which is usually used to enable external address decoding, a little later to allow easy decoding without address line glitches, and \$\overline {RD}\$ active, which is usually used to enable the memory to CPU data buffers, also later to allow easy implementation without bus contention.

The CPU will not attempt to read the data until halfway through \$T_3\$, the memory must have managed to return settled valid data to the CPU by \$T_{DS}\$ before this, let's call this total delay the memory system access time.

From this diagram, YOU must design a memory system, where the delays of the address decoder, the memory IC's access time, and the return data buffer together must be less than the memory system access time.

Hint, CPUs are usually designed to work with logic and memories available when they're produced, there would be little point producing a CPU which did not have the rest of the system available. So you should be able to find memory components in the same sort of price range as the CPU that meet the timing specifications.

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The address must be held constant on the bus for a long time in order for the memory to be able to use it. This period starts at the end of TAD and must last at least until MREQ- goes high. The period between the end of TAD and the start of TDS (data setup) is called the address access time of the memory. This time gives the logic inside the memory (address decoders, the memory array itself, and the output multiplexers and drivers) time to do their thing in order to put the correct data on the bus.

In other words, the memory access starts when there's a valid address on the bus and MREQ- goes low.

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  • \$\begingroup\$ Also note here the Addr. bus and _WAIT uses rising edge of clk and the falling edge is used for edges of _MREQ, _RD and latching stable Data bus. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 29 '17 at 3:33
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" In the image, the data is read before the address was completely loaded."

Say what? This simply isn't true.

The address is stable on the CPU/memory buss after TAD of T1. It is loaded into the memory by the falling edge of MREQ and RD during the second half of T1. The address remains stable until well after the data becomes available during T3. The address can change while the data remains stable, but this simply reflects the internal delays in the memory from address to data.

In this case (and in any memory read) from the point of view of the memory the address is an input and the data an output. If the situation were as you described ("data is read before the address was completely loaded"), this would constitute reading the future. Instead, the address is present and stable for about 2 full clock cycles before the data is available.

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