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Having read this comment, I'm a bit concerned about whether one of my projects is going to work:

schematic

simulate this circuit – Schematic created using CircuitLab

The comparator is also inside the uC, but shown explicitly for clarity.

The intent of this question appears to be an exact duplicate, but its only answer completely misses what I think is a critical point: The transformer is (almost) completely unloaded at the time that I want the ZCD pulse.

I can understand that having both linear and reactive components, considering the transformer and the load together, can cause a load-dependent phase-shift, and that's what the other answer was about. But in my case, and in the case of the other question, the transformer becomes unloaded for all except the peaks, and we want to sense the zeros. Given that detail, is there still a phase-shift to worry about between the primary zero-crossing and the secondary one?

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  • \$\begingroup\$ @Transistor I meant the load was effectively open-circuit. Yes, you're correct about the transformer itself. Duly edited. \$\endgroup\$ – AaronD Jun 29 '17 at 7:57
  • \$\begingroup\$ In that case, why don't you directly observe the mains via an optocoupler (bristolwatch.com/ele2/zero_crossing.htm)? In your case, there are lot of parasitics (especially those of the diodes) which are not accounted for in the simulator. All these nicely-showing sine waves are in reality distorted signals (especially from the ac outlet depending where you are) and nothing replaces the experiment in your case. \$\endgroup\$ – Verbal Kint Jun 29 '17 at 8:06
  • \$\begingroup\$ @VerbalKint I did use opto's for a previous design, and it worked flawlessly...except for the 5.6k resistors getting hot because they were directly across the mains. (don't do that again) I could use an opto on the secondary side, but then I have the same potential phase-shift as anything else on the secondary side. The question is whether that phase-shift actually exists. \$\endgroup\$ – AaronD Jun 29 '17 at 8:15
  • \$\begingroup\$ I see your point. This one seems to deal with much lower currents though (edn.com/design/analog/4368740/…) and could work in your case. As I said, now that you have simulated your circuit, time to power the soldering iron and check the waveforms : ) \$\endgroup\$ – Verbal Kint Jun 29 '17 at 8:21
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In an ideal transformer, the primary voltage and the secondary voltage are identical (except for scale) at all times. This is because it's the changing flux in the core that creates the voltages on all the windings.

When we introduce reality into the transformer, it disturbs that slightly. The finite primary inductance means the transformer draws a magnetising current, in quadrature phase to the input voltage. The finite winding resistance means that the magnetising current creates a small voltage in quadrature phase to the input voltage. This creates a small phase offset between the primary and secondary voltages. The load currents are in phase, and so irrelevant.

The phase error in a good transformer is small. It will be significant if you're trying to make a precision lab instrument for measuring phase shift. It should not be significant if you're triggering a zero-cross switching circuit, or phase-shift Triac dimmer, try it and see.

Note that transformers get better as they get bigger. A 'good' transformer may have to be a big transformer, say 50VA and up. It's likely that PCB mount matchbox-size and down could be too non-ideal for this use.

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  • \$\begingroup\$ I have experience with small pcb mount transformers . The deformation of the sinewave, not the phase error is the main problem. \$\endgroup\$ – Decapod Jun 29 '17 at 16:34
  • \$\begingroup\$ I'll go ahead and accept this answer because it explains the most relevant detail, but it looks like I'll have some trial-and-error adjustment once I get it built. \$\endgroup\$ – AaronD Jul 8 '17 at 19:55
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Zero Crossing

Realize the zero crossing first without transformer. Separate optical. See this old elektor design. The value of C1 is crucial. The received puls can be send to the micro processor. I have realized this circuit many times and it works without a flaw.

A short quote from the old Elektor magazine: Due to reactive, non-uniform loads, zero crossing points can be exactly determined on the secondary side of the transformer only under certain conditions. The non-linear transfer characteristic often causes the secondary voltage to be deformed and offset in phase, so it cannot be assumed to be a clean, phase-aligned sine-wave signal.

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  • 1
    \$\begingroup\$ I've love to see a much better schematic layout for that circuit, designed for understanding the important details. What's there is probably directly from Elektor and a pretty bad layout if one wants to communicate the design features well. For example, \$D_3\$ serves two completely different and important functions depending on the half-cycle. One of them is to protect the BE junction of \$T_1\$ and is vital. But it's not easy to notice unless you know to look for it. Could you consider a better layout and analysis for both half-cycles? \$\endgroup\$ – jonk Jun 29 '17 at 17:05
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The transformer is never open-circuit. The output is zero at zero-cross, if that's what you mean.

schematic

simulate this circuit – Schematic created using CircuitLab

Figure 1. Simplified schematic. D1 allows monitoring of the full-wave rectified signal for zero-cross detection.

With this arrangement your comparitor will switch slightly before and after zero-cross. You can measure the time of this pulse, divide by two and apply that timing offset in your code to be close to the true zero-cross.

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  • \$\begingroup\$ But is the secondary zero-cross guaranteed to be in-phase with the primary zero-cross? That's really the question. \$\endgroup\$ – AaronD Jun 29 '17 at 8:10
  • \$\begingroup\$ @AaronD to within the accuracy that you want it, yes, the primary and secondary voltages are precisely in phase, especially because there are no load currents flowing to generate errors. There is the primary magnetising current flowing, which will cause a shift, but that's small in a well designed transformer. \$\endgroup\$ – Neil_UK Jun 29 '17 at 8:12
  • \$\begingroup\$ @Neil_UK It seems to me like you've got an answer. If you'd like to make it one, I'll at least upvote if not accept it. \$\endgroup\$ – AaronD Jun 29 '17 at 8:32
  • \$\begingroup\$ @Neil_UK. I have been using BLOCK pcb transformers. They do not have a nice output as is required by your comment. I prefer the cross detection on the mains side and separate optically. See my answer. It works without a flaw. \$\endgroup\$ – Decapod Jun 29 '17 at 8:37
  • \$\begingroup\$ @Decapod Can you please elaborate on how to spot those transformers and how they don't work? Seems to me like a prerequisite to your answer. \$\endgroup\$ – AaronD Jun 29 '17 at 8:45
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This circuit won't work, but the reason is a bit subtle, and you guys all got it wrong ;)

I'll simulate it.

schematic

simulate this circuit – Schematic created using CircuitLab

The trick is to wonder what exactly sets the potential of points "AC1" and "ACD" relative to our post-rectifier ground? The answer is that it depends on what diodes actually conduct, and if they are off, it depends on their leakage currents.

Fortunately, you made it... umm, simpler by including a second bridge rectifier. Now, here, obviously R3 and R4 conduct some current almost all the time, which biases one of D10/D11 (and D12/D13) into conduction also. The result is that AC1 and AC2 relative to GND become this:

enter image description here

Unfortunately, the voltage on the "COMP" node relative to GND (which is what your comparator sees) is the minimum of these two (minus a diode drop) and thus is not what you'd like at all to detect any kind of zero cross......

enter image description here

This won't work, not because of phase shift, but because both bridges interfere and the waveform is just... wrong.

Now, what if we remove the second bridge ?

schematic

simulate this circuit

enter image description here

Very nice! Since the diodes constrain AC1 and AC2 to be between GND and VCC (modulo diode drops), all we have to do is to feed AC1 and AC2 to the inputs of our comparator, with adequate input protection resistors of course, and it will then detect the zero crossing.

Now, what is RLeak? In the previous simulation, it was omitted. But of course one diode will leak more than the others, which our neat simulation did not account for, since all diodes were exactly identical. Adding RLeak to account for this means the waveforms on AC1 and AC2 will be more like... this...

enter image description here

Amusingly, a comparator between AC1 and AC2 would still work...

The Elektor solution posted by Decapod is much better, since it negates transformer phase shift. But it needs more parts. Your choice!

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  • \$\begingroup\$ "... and you guys all got it wrong ;)". Steady on, old chap. \$\endgroup\$ – Transistor Jun 29 '17 at 18:21
  • \$\begingroup\$ It sounds like you might be on to something, but for whatever reason, I'm not getting images, including some in other Q's and A's that worked last night. But some of them still do work, so go figure. I'll try again later. \$\endgroup\$ – AaronD Jun 29 '17 at 21:17
  • \$\begingroup\$ Okay, I've got images now. And it looks like your analysis lines up with mine in terms of what the COMP waveform should look like and why. But I was going to compare that waveform against a suitable DC level that is generated from the internal DAC. (I'm at a premium for pins on this uC, and this only requires one actual input to the internal comparator compared to two) On your plot, a 3VDC threshold might be a decent starting point, and would generate a finite-length pulse that is exactly centered on the actual zero-crossing, correct? \$\endgroup\$ – AaronD Jun 30 '17 at 6:55
  • \$\begingroup\$ The reason to have a finite-length, centered pulse instead of an immediate edge, as from comparing AC1 and AC2, is to allow some wiggle-room for interrupt latency and the slight extra overhead of handling a zero-crossing event. So I'm planning on using a timer overflow for the actual zero-cross interrupt, which is automatically adjusted by the comparator interrupts that are nicely out of its way. (At the trailing edge, the timer should be the 1's complement of what it was set to at the leading edge; adjust the setting accordingly.) Somewhat-sorta like a software PLL. \$\endgroup\$ – AaronD Jun 30 '17 at 7:01

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