Noisy RLC circuit

I have made a printed circuit board to test different inductor and capacitor values at their resonant frequencies. I am trying to measure voltage drop when two coils are resonantly coupled at different distances. It is a primitive RFID reader with no data transfer.

When the coil isn't driven, ripple on LM317 (powered from a switched-mode power supply) is small, below 100mV(node 1). When I connect coil and drive MOSFET with function generator I get a sine wave but, the amplitude of the sine is not constant. The voltage from LM317 is 3V, with potentiometer set to 10 Ohms the peak voltage is about 10V. Amplitude varies around 500mV, Noise on the Power supply is more visible(node 1).

So I observe a waveform at node 2, which varies between 10V and 9.5V on positive cycle, ten seconds later it changes to 10.2V and 9.7V, later on, its 9.8V and 9.5V, it keeps changing around that 10V.

I think the reason why this happens, is because the capacitors are not able to supply nessecery power to drive a load at that frequency. I was looking around the internet for equations to calculate a proper capacitors values, but with no luck. Or maby LM317 is a poor choice for regulator when driving transient load? Any ideas on how to improve this circuit to have nice stable voltage on envelope detector?

EDIT: R5 potentiometer serves a purpose of increasing or decreasing damping factor and bandwidth of RLC. D1, C2, R2 forms peak detector to measure signal amplitude.

simulate this circuit – Schematic created using CircuitLab

• (1) "So I observe a waveform ..." Where? Edit your schematic and add NODEs and reference these in your text when listing the voltages at various points. (2) What is the 100 $\Omega$ pot supposed to do? It will ruin any voltage regulation you hoped for. (3) What is D1, C2 and R2 for? Jun 29, 2017 at 20:32

1 Answer

I would be concerned that the signal generator is not capable of reliably driving the FET due to gate capacitance. Also, a resistor between the gate and source would assist with turn-off but you should consider a proper gate driver .

It would be good to increase the decoupling between the circuit and the PS. A large value RFC would be one method.

Be careful with your measurement at the LC junction. Any parasitics have the potential to greatly distort the observations.

• actually, my design included TC4424 Mosfet driver at the beginning, it was connected before the voltage regulator, but loading of driver increased noise so I got rid of it. When using Mosfet driver should I use gate resistor as well? Is there any formula for calculating choke value?. Jun 30, 2017 at 7:44
• The FET driver output should be rated to drive the FET gate capacitance with a rise time sufficient for your application. I recommend at least a 50% safety margin for the gate capacitance spec.The input of the driver must be compatible with your clock source. For the RFC, I would recommend a Spice model and start with 5-10k impedance at your switching frequencies and adjust from there. Jun 30, 2017 at 11:22