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I've been designing a noise generator (for fun) with the goal of getting a smooth frequency response between 10Hz and 10MHz. Since I don't have any "fancy" op-amps, I decided to go with a discrete design that will eventually use a cascade of cascode amplifiers. I the first stage, I would like to use a single zener to bias the amplifier and act as the noise source.

Design Notes:

  • I chose the cascode amplifier because it is not subject to the miller effect
  • In order to take advantage of the avalanche effect, Vz > 6.5V (the 1N4737 drops 7.5V @ 30mA)
  • One option is to use the zener only as a noise source, and perform the biasing separately, but I would prefer not to take this route
  • The 1N4148 is used only for biasing and can be replaced with a resistor if necessary
  • The transistors are set to have a bias current of 10mA (max gain point for the 2N3904)
  • I realize op-amps can be used to do the same thing, but I wanted the additional challenge of coming up with a discrete design, and op-amps with a 100MHz bandwidth don't come cheap.

Noise generator 1st stage schematic

Noise generator 1st stage frequency response simulation

Questions:

  • Does my simulation provide a good approximation of the desired behavior? Recall that the goal is to amplify white noise between 10Hz and 10MHz.
  • How can I reduce the value of the emitter bypass capacitor (C2) while maintaining the desired frequency response and passband gain?
  • If I were to build this circuit using an aluminum electrolytic capacitor for C2, will I run into ESR problems at high frequencies?
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  • \$\begingroup\$ Besides adding realistic parasitics to basically every component, you should also do some transient analysis with a frequency sweep and with noise input and look at the FFTs and make sure you do it as accurately as possible, audio-perfection.com/spice-ltspice/… gives some nice hints. \$\endgroup\$ – PlasmaHH Jun 30 '17 at 10:08
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If I were to build this circuit using an aluminum electrolytic capacitor for C2, will I run into ESR problems at high frequencies?

Not only ESR but ESL (inductance) will cause a resonant frequency and a gain peaking somewhere in the mid kHz to tens of kHz range and above this, gain will gradually reduce as the inductor becomes more dominant.

How can I reduce the value of the emitter bypass capacitor (C2) while maintaining the desired frequency response and passband gain?

Difficult given that you need a gain of ten and that you don't want the output impedance to rise much more than 680 ohms - I would consider using ceramic 22 uF capacitors and parallel them up to give you 220 uF. Again, you have to watch out for resonant frequency problems and you may need to add some 100 nF capacitors across those 22 uF caps to get a fairly flat response.

Try looking up a few and adding the parasitic components to your model. So, to answer your first question: -

Does my simulation provide a good approximation of the desired behavior? Recall that the goal is to amplify white noise between 10Hz and 10MHz.

No, but this is easily remedied by adding parasitic components.

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  • \$\begingroup\$ How would I choose parasitic component values? \$\endgroup\$ – Caleb Reister Jun 30 '17 at 13:38
  • \$\begingroup\$ You need to look at the data sheets for a capacitor that might be worth considering. It should be a capacitor that has enough data in order to realize the internal parasitics such as R and L. \$\endgroup\$ – Andy aka Jun 30 '17 at 13:44
  • \$\begingroup\$ Based on that advice, I think I'm just going to use my alternate configuration that biases using resistors a doesn't require large capacitor values. \$\endgroup\$ – Caleb Reister Jul 3 '17 at 2:18
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Let's flip that circuit around

schematic

simulate this circuit – Schematic created using CircuitLab

Your power supply rejection is much improved.

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  • \$\begingroup\$ Can you explain the changes? Also, that design uses a much lower voltage zener. \$\endgroup\$ – Caleb Reister Jun 30 '17 at 13:51

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