Hello I have done a bit of research on google and on SE about how much power a FPGA uses and the answers are all unacceptable in my opinion.

Therefore I am going to ask in another way.

I need a generalized statistical analysis of the average power consumption to expect for all of my future FPGA related projects.

I need just a ballpark figure so that I can use that information when making decisions about more specific elements of a project involving an FPGA

I do not particularly care about actual real world parts, nor the manufacturers of those parts. I also do not care about getting an exact number.

My preliminary research seems to suggest 90% of FPGA devices can be expected to operate between 10 to 100 watts. And to obtain detailed information would require designing a project around a specific FPGA as the variance can be much more or much less with certain chips in certain arrangements.


closed as too broad by brhans, horta, Lorenzo Donati, DoxyLover, Enric Blanco Jul 1 '17 at 10:09

Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

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    \$\begingroup\$ Your question has a simple answer. You have to know a little about the model for calculating core temperature, which is related to dissipated power, thermal resistance and maximum ambient operating temperature of the device. Thermal resistance is calculated using the device thermal resistance and that of any disipators you may have used. If the temperature of the core doesn't go above the max. admitted temperature according the datasheet, you are safe. Be aware that nowadays FPGA can easily take in the order 10-20W. Until you give more details, that is the best answer I can give you. \$\endgroup\$ – Claudio Avi Chami Jun 30 '17 at 17:43
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    \$\begingroup\$ It would help if you gave us the specific FPGA you are going to use! Otherwise, speaking so generally will be a bit difficult. \$\endgroup\$ – nickagian Jun 30 '17 at 17:45
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    \$\begingroup\$ Absolute minimum: 0 Absolute maximum: Use the power estimator and give it worst-case inputs. \$\endgroup\$ – The Photon Jun 30 '17 at 17:54
  • \$\begingroup\$ If you want the "smoke number" look at the package specifications. Your max ambient temperature, the chip max junction temperature and the cooling (either with or without a heatsink) should answer that question. Then also look at the requirements of various (core) voltage rails to get your final power budget answer. \$\endgroup\$ – Hans Jun 30 '17 at 18:24
  • \$\begingroup\$ Well a specific FPGA, im really not sure what to pick, can you tackle a couple? Maybe a Zync7-ish vs a AT40K-ish \$\endgroup\$ – pfifo Jun 30 '17 at 18:24

In addition, pointing me to the power estimator utilities doesn't help to solve my problem as I'm in such an early stage in development, that I don't have the info required to make the sheet give useful information.

If you want a worst-case power estimate, just plug in worst-case values.

All clock management blocks active at maximum frequency. All logic occupied and switching with 50% transition density at maximum frequency. All DSP blocks, Multiplier blocks, SERDES blocks, etc., operating at maximum frequency. All IO used and outputting with the worst-case logic standard at maximum frequency with 50% transition density.

No number anybody can give you will be any more useful than the one you get this way.

Alternatively, do more work on your design until you can get a better estimate of the resource requirements, then feed that to the estimator tool.

What I want to know is the range between absolute minimum power consumed to the absolute maximum power consumed for various popular FPGAs

The minimum power consumed isn't very interesting. That's just the case where the device is unprogrammed or you've programmed it with a single flip-flop that never changes state.

If you really need a value (say, because your power supply has a minimum load to maintain regulation), use the estimator tool and specify no resources used. I looked at one estimator spreadsheet from Altera(Intel) and they specifically report a static power consumption --- so use that.

In any case your device will be in the unprogrammed state briefly every time you turn it on, so your power system will need to handle it.

I'm ... interested in ... how much power the device itself can theoretically consume before it disintegrates in a blinding flash of smoke.

You can work this out from the package thermal data. For example, looking at the data for various packages available for Altera's high end FPGA's (here), the minimum \$\theta_{JA}\$ value is about 4 C/W (with maximum airflow). If we want to keep the junction temperature below 100 C with 40 C ambient, that means we need to keep the power consumption below about 15 W.

But if you're really desperate you might consider adding external heat sinks or even water-cooling your FPGA.


The design decision of using or not using an FPGA being based on power consumption. With no prior experience with any FPGA at all, I need some sort of scale to determine if I should further investigate using an FPGA, or fall back to a slower MCU for the processing.

In this case, the maximum power possible to use in an FPGA is totally irrelevant, and you need to do more study about how much power would be needed to solve your actual problem.

The usual reason to choose an FPGA over an MCU isn't to save power (it won't); it's to achieve a required throughput (calculations per second) or to maintain control of the latency in the calculations. An FPGA can achieve greater throughput than an MCU for many problems due to its ability to do many calculations in parallel.

If your problem is solvable by an MCU, that will typically be the lower-power and lower-cost solution, and you should choose the MCU. It's when you find a problem that an MCU can't keep up with that you'll turn to the FPGA.

  • \$\begingroup\$ When I say ball park, i really am asking someone to set the scale for me. At this point, all I can draw with any absolute certainty is that and FPGA uses less than 1800 watts of power. The reasoning for this is that the wall outlet can only provide 1800 watts maximum, and the only device I have with an FPGA plugs into the wall. Any refinement to that number would be insanely helpful! Im dead serious, it would be a massive help to know some sort of maximum. I dont understand why people are so afraid to throw out a chart or a few numbers here. \$\endgroup\$ – pfifo Jun 30 '17 at 18:19
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    \$\begingroup\$ @pfifo, because the result depends dramatically on the resources used by your design. A low-power fpga with 2 or 3 active IO's might need 2 mW. A high resource FPGA used for ASIC simulation with 1000 active IO pins might need 10's of watts. \$\endgroup\$ – The Photon Jun 30 '17 at 18:26
  • \$\begingroup\$ 10's of watts, that is the perfect answer. thanks so much \$\endgroup\$ – pfifo Jun 30 '17 at 18:31
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    \$\begingroup\$ @pfifo, you don't understand because you don't seem to made any effort to understand the underlying technology. The answer depends on the number of switching gates in a design, on particular fabrication node, and on frequency of switching of those dynamic gates. As Photon said, it could be 2mW. The upper limit is set by heat-transfer limitations of modern packages, which is about 100W per chip in normal technology. \$\endgroup\$ – Ale..chenski Jun 30 '17 at 18:36
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    \$\begingroup\$ @pfifo - You can't even say that it will use less than 1800 Watts because you haven't determined that the problem will fit into a single FPGA. Some problems may take many, many FPGAs and need many kilowatts of power. There is no limit if you have a hard enough problem to solve. \$\endgroup\$ – Kevin White Jun 30 '17 at 20:37

The answer depends on the number of switching gates in the design, on particular fabrication node of FPGA IC, and on frequency of switching of those dynamic gates. As Photon said, it could be 2mW, if it is running at 32kHz and has only few actively-switching flops. Or it could be much more if there are many parallel IP blocks/SERDESes running at GHz++ rate.

The upper limit however is set by heat-transfer limitations of modern packages, which is about 100W per chip in normal technology.

To get more accurate estimate, you need to compile your RTL for a particular FPGA family, and run their power estimator.

Alternatively, you can research offerings of development boards of various grade and sizes. These platforms are usually made to accommodate worst case of digital applications and maxing out product capabilities. You then can examine what kind of power supply is placed on these boards by platform designers, and it will give you a ballpark estimate how much power is required by your selected FPGA.

  • \$\begingroup\$ Thats some really good info, using stats from the dev board to help select the chip to use in the first place. Thanks \$\endgroup\$ – pfifo Jul 1 '17 at 16:40

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