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Suppose that I have two processes in VHDL: One process is triggered on the rising clock edge and it is a state machine that sets a flag in one of its states. The second process is also triggered on the rising clock edge and it has a condition statement that reads this flag to see if it is '1'. When will the condition in the second process become 'true'? On the same clock that the flag is set, or at the next clock?

Here is an example:

-- state machine 
process (clk)
begin
    if rising_edge (clk) then       
        case StateMachine is
            when '0' =>
                flagA <= '0';
                StateMachine <= '1';
            when '1' =>
                flagA <= '1';
                StateMachine <= '1'; -- loop forever
        end case;
    end if;
end process;

-- condition
process (clk)
begin
    if rising_edge (clk) then       
        if (flagA = '1') then
            flagB <= '1';
        else
            flagB <= '0';
        end if;
    end if;
end process;

In this example, will flagB become '1' at the same clock that flagA became '1'? Or will flagB become '1' at the next clock?

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  • 3
    \$\begingroup\$ For the future – it would be worth checking by yourself on simulator. It is much more valuable for learning to do and see something, than to ask. And this is quite easy to check. \$\endgroup\$ – Staszek Jul 2 '17 at 11:53
  • \$\begingroup\$ This is because you use the one process form of the FSM pattern. It adds additional (and mostly unwanted) output registers. \$\endgroup\$ – Paebbels Jul 2 '17 at 17:50
  • \$\begingroup\$ In the second process, you are just assigning glagA to flagB. Just do that; no if/then required. Similarly for the first process. \$\endgroup\$ – Brian Carlton Jul 10 '17 at 18:22
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Flag state will be sampled on the next clock edge. In the synchronous design, all the conditions are (or must be) "prepared" before clock edge occurs, and when it occurs, circuit transitions to new state within very short timeframe. Thus in situations like yours circuit will see previously "prepared" condition, thus previous state of the flag. On the next clock edge new flag value will be "prepared", and it will be sampled.

You spend whole cycle to get the new propagated flag value; you may consider to trigger one process on rising edge, and another process on the falling edge, this way you will spend only half of the cycle.

Update (as per comments below): when designing circuits driven by both edges of the clock, you must pay close attention to the duty cycle of the clock, not just its period.

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  • 3
    \$\begingroup\$ I would not suggest dual-clock edge logic. Not unless you are designing very high speed logic. Just put everything in a single synchronous process, or make the second process combinatorial. \$\endgroup\$ – JHBonarius Jul 6 '17 at 11:04
  • \$\begingroup\$ I agree with JHBonarius. Dual-clock edge can trigger problems if it is not designed corectly. \$\endgroup\$ – e2p Jul 10 '17 at 13:24

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