# VHDL assignment and condition at the same clock edge on parallel processes

Suppose that I have two processes in VHDL: One process is triggered on the rising clock edge and it is a state machine that sets a flag in one of its states. The second process is also triggered on the rising clock edge and it has a condition statement that reads this flag to see if it is '1'. When will the condition in the second process become 'true'? On the same clock that the flag is set, or at the next clock?

Here is an example:

-- state machine
process (clk)
begin
if rising_edge (clk) then
case StateMachine is
when '0' =>
flagA <= '0';
StateMachine <= '1';
when '1' =>
flagA <= '1';
StateMachine <= '1'; -- loop forever
end case;
end if;
end process;

-- condition
process (clk)
begin
if rising_edge (clk) then
if (flagA = '1') then
flagB <= '1';
else
flagB <= '0';
end if;
end if;
end process;


In this example, will flagB become '1' at the same clock that flagA became '1'? Or will flagB become '1' at the next clock?

• For the future – it would be worth checking by yourself on simulator. It is much more valuable for learning to do and see something, than to ask. And this is quite easy to check. – Staszek Jul 2 '17 at 11:53
• This is because you use the one process form of the FSM pattern. It adds additional (and mostly unwanted) output registers. – Paebbels Jul 2 '17 at 17:50
• In the second process, you are just assigning glagA to flagB. Just do that; no if/then required. Similarly for the first process. – Brian Carlton Jul 10 '17 at 18:22