I have recently become fascinated by asynchronous CPUs, which have no central clock and each module instead sends a signal, when their data has been processed. However, I have been wondering how such modules actually know when their output is ready and stable?
In the following example of an asynchronous sequential circuit, some modules communicate using a simple handshake protocol as follows:
- A module is triggered by a READY signal from a previous module.
- The module then starts manipulating the input data.
- The RECEIVED signal is sent to the previous module, when the input has been read and can be modified by the prevous module.
- When the output is updated and stable, a READY signal is sent to the next module.
- When the RECEIVED signal is sent as a reply, the process starts over.
- Is it possible to send a READY signal when the output of a module is stable, without specifically timing the propagation delay of the module circuit?
- If not, what would be the simplest way of delaying a READY signal based on a circuit's worst case propagation delay?