We created a circuit with diode array for ESD protection PN: IP4283CZ10-TBR (MFR: Nexperia)

Data sheet

As you can in the datasheet, there are some pins which supposed to be N.C, but we did connect them to the signal pins, as you can see here: enter image description here

We afraid that this connection might explain some problems we see in our samples, for example- one PCB didn't communicate with UART until we removed the part and another circuit failed during first watchdog test (again, until we removed this part).

In the datasheet all I could find that is related to the N.C pins was this line that mention that the capcitance between N.C pin to signal pin is 0.07pF (sorry, can't upload another image)

Correct me if I'm wrong, but it doesn't say much (just that the pins are seperated using small value CAP, nothing about not short between them).

Hope you could help me understand if this what is causing the problem or is it something else. We also use another 3 identical diodes arrays with same "connection problem", but they seem to work fine (Connected to RS422 RX,TX and Debugger lines)

The debugger we are using is J-LINK (using JTAG communication).

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    \$\begingroup\$ As shown in figure 1, you are supposed to connect the signals like this. Did you test whether the removed devices actually work? \$\endgroup\$ – CL. Jul 2 '17 at 14:05
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    \$\begingroup\$ Is the signal reference ground at the processor on the JTAG port the same as your chassis dgnd? \$\endgroup\$ – Peter Smith Jul 2 '17 at 14:08
  • \$\begingroup\$ Hi Peter, actully no, it is not the same GND. Do you think it might be a problem? those grounds are sepereated with 220k (and 3nF in paralell) between them. \$\endgroup\$ – Dudi Jul 2 '17 at 14:43
  • \$\begingroup\$ I think you'll may want to change your number for the capacitance value between N.C. and signal. Datasheet says it's 0.07 pF \$\endgroup\$ – nickagian Jul 2 '17 at 17:35
  • \$\begingroup\$ @CL. I don't think you have right. Figure 1 does not show that the signals are to be connected like the OP did. It just shows that the package pads are so oriented that from the two pads directly opposite each other only one is active (connected internally to diodes). In this way one could route the signal in a straight trace below the package without an interception from another trace connection. \$\endgroup\$ – nickagian Jul 2 '17 at 18:23

When listed in a datasheet, "No connect" can mean "Don't connect this pin!" or "We didn't connect this pin.". This looks like the latter. The 0.6 pF is just parasitics, and picofarads will not affect a UART or reset.

Your problems are most likely unrelated to these connections. Since you're seeing differences between copies of supposedly identical boards, there are probably manufacturing or assembly defects (but this isn't 100% certain - could also be marginal design). I would start with a thorough visual inspection under a microscope looking for soldering shorts and opens. Check polarity / pin 1 position of all active devices.

Maybe when you removed this part from your defective boards, you also reflowed some other nearby parts.

  • \$\begingroup\$ Thought about it, but nothing I could find that can explain that. Maybe it is more relater to what Peter suggested? Differnces between GNDs? I have 3 different GNDs here- 1 of the JTAG and microprocessor, one for this ESD diode and another one for the other 3 ESD diodes (which are fine) \$\endgroup\$ – Dudi Jul 2 '17 at 14:46
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    \$\begingroup\$ why is the ground of your device which you want to protect not the same as the gnd of your ESD diode? \$\endgroup\$ – Andy Jul 2 '17 at 14:53
  • \$\begingroup\$ The ESD diode should protect the Chassis GND which is the metal case that covers our circuit \$\endgroup\$ – Dudi Jul 3 '17 at 6:16
  • \$\begingroup\$ A simple experiment would be to tie the ground of the device being protected to chassis so the diodes share the same ground. \$\endgroup\$ – Peter Smith Jul 5 '17 at 16:21

From the datasheet I get the impression that these N.C. pins are really just not connected internally. And this 0.07 pF between these pins and the signal pins are probably just parasitics (although I don't quite understand why they state the value of such parasitics).

Anyway, my point is that I don't think you have any problem with the connections that you have made.

An idea that may apply in your case is that perhaps this diode array that you removed from the boards that didn't work as intended was defective (perhaps destroyed during soldering) and for this reason it affected the signals connected to them. So when you removed the defective part the circuit worked ok.

  • \$\begingroup\$ Might be. Thank you all, I will look for another direction... \$\endgroup\$ – Dudi Jul 3 '17 at 6:17

looks painfully familiar. If i understand you correctly, your device occasionally would not run properly until you removed diodes, right? It seems to be tricked @poweup into JTAG/Debug mode by those diodes. you need different diodes for esd protection

  • \$\begingroup\$ Setting aside the fact that this question is from a year and a half ago, your answer would benefit from an explanation of why you believe that these diodes (which are designed for ESD protection), are not suitable for ESD protection in this case. \$\endgroup\$ – Blair Fonville Oct 27 '18 at 3:52

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