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I came across circuits probably using an AC at the base to probably amplify it. I also came across the voltage divider to add a DC bias.

schematic

simulate this circuit – Schematic created using CircuitLab

Neglecting the values of the components and supplies. Is the reason we add this DC bias to not have the voltage go to a negative value because that would damage a transistor?

And just to be sure, the voltage at the base would be a sine wave with the DC bias as the baseline, correct?

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Neglecting the values of the components and supplies. Is the reason we add this DC bias to not have the voltage go to a negative value because that would damage a transistor?

The reason for the DC bias is to ensure the transistor stays in the linear region and therefore works as an amplifier.

The idea with biasing is that you set the DC operating point of an amplifier somewhere in the linear region, preferably in the middle, and you superimpose a "small" varying ac signal so that it gets amplified. If the signal isn't small enough, you may end up steering your transistor out of the linear region, it will no longer work as an amplifier.

Take a look at the following graph. If you bias the transistor so that it works in active mode, you can utilize it to amplify small varying signals. In the graph \$v_{be}\$ is the ac signal to amplify and \$V_{BE}\$ sets the DC bias point and the amplified signal output is \$v_{ce}\$.

And just to be sure, the voltage at the base would be a sine wave with the DC bias as the baseline, correct?

Yes. You essentially have \$V_{BIAS}+v_{ac}\$ at the input. That's why the input signal has to be small enough so that you don't disrupt the DC bias point.

enter image description here

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  • \$\begingroup\$ Thanks for the reply. So I believe that typically a transistor enters the saturation mode, after Vb becomes greater than Vc or in other words both diode become forward biased. In the graph above, how is the dotted line entering the saturation region plotted ? I mean, what is setting that region to be the saturation region ? (I don't see that voltage marked on the x-axis. I am assuming it is Vc ? \$\endgroup\$ – Dennis Tyler Jul 2 '17 at 23:18
  • \$\begingroup\$ @DennisTyler The x-axis represents the base-emitter voltage, which equals the the base voltage since the emitter is grounded. The y-axis represents the collector-emitter voltage, which equals the collector voltage. You are correct, in saturation both junctions are forward biased (VBE>0,VBC>0). \$\endgroup\$ – Big6 Jul 2 '17 at 23:41
  • \$\begingroup\$ @DennisTyler The point on the x-axis, which represents entering the saturation region, is just a point where VBE>VCE (same as saying VB > VC for the circuit in the picture), they don't need to quantify it (i.e. show a specific number) this is just a qualitative representation. In saturation, though, VCE \$\approx 0.3\$V which makes VBE greater than that and therefore saturation (0.5V is shown on the graph near the cutoff region so VBE>0.5 when VCE=0.3V). \$\endgroup\$ – Big6 Jul 2 '17 at 23:42
  • \$\begingroup\$ Thanks for clearing that up. Can I ask you the source for the image ? \$\endgroup\$ – Dennis Tyler Jul 3 '17 at 0:16
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    \$\begingroup\$ @DennisTyler Microelectronic circuits 6ed, Sedra-Smith \$\endgroup\$ – Big6 Jul 3 '17 at 1:18
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Here is a self-bias circuit for a bipolar, guaranteed to place the bipolar in the "linear" region

schematic

simulate this circuit – Schematic created using CircuitLab

With ZERO source impedance (and huge input cap) the voltage on the base will be pure-sine, and the 4mVpp/10% distortion is accurate. With large Rsource, the voltage division action converts that voltage into more of a current-source and if the beta is "linear" the collector current will be linear, while the Vbase will be logarithm of the base current.

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  • \$\begingroup\$ Thanks for that circuit, but it doesn't really answer my question. \$\endgroup\$ – Dennis Tyler Jul 2 '17 at 20:45
  • \$\begingroup\$ Read the final paragraph; the base waveform will not be a pure sin if there is any Zsource (including the DC_blocking cap) \$\endgroup\$ – analogsystemsrf Jul 3 '17 at 3:12

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