I need help in understanding the solution from solution manual. The question is from the exercise 4.22.1 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition). The question is about branching in instruction pipeline.
We assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor. Consider the instruction sequence:
Label1: LW R2,0(R2)
BEQ R2,R0,Label ; Taken once, then not taken
Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage.
The solution given is as follows:
I dont understand why in 4th cycle
*** (blue underlined). Cant we execute
LW in 4th cycle? Is it unsaid rule that if the branch-decision-making-stage (that is red underlined
BEQ) gets delayed (here due to data dependency on first
R2), then delay all the corresponding next stages in the following instructions?