Understanding instruction branching

I need help in understanding the solution from solution manual. The question is from the exercise 4.22.1 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition). The question is about branching in instruction pipeline.

The question
We assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor. Consider the instruction sequence:
Label1: LW R2,0(R2)
BEQ R2,R0,Label ; Taken once, then not taken
OR R2,R2,R3
SW R2,0(R5)
Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage.

The solution given is as follows:

The solution

The doubt
I dont understand why in 4th cycle LW have *** (blue underlined). Cant we execute ID of LW in 4th cycle? Is it unsaid rule that if the branch-decision-making-stage (that is red underlined EX of BEQ) gets delayed (here due to data dependency on first LW for R2), then delay all the corresponding next stages in the following instructions?

• ok I think there is something more that added to my confusion: 3rd instruction LW is fetched immediately after 2nd instruction BEQ. But that is not the case with OR. It is fetched far after when preceding BEQ is in MEM stage. Is the LW still fetched after 2nd BEQ, before OR, but because prediction went wrong it was abandoned and OR` is fetched? Something like this:image – Maha Jul 4 '17 at 5:05