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I'm putting together a simple DTACK circuit for a 68k homebrew machine, and part of that is requires me to know when either the Upper Data Strobe (UDS) or Lower Data Strobe (LDS) is asserted LOW. I've only got a few random ICs to hand, so I'm attempting to use a 7408 AND and driving the output into two inputs of a 7402 NOR gate.

For some reason the output of the AND gate seemingly isn't correct, it seems to miss pulses and I don't know why. It's a fast chip and I believe we're way within it's tolerances so what should I be looking for?

The output below from my logic analyser shows 3 address lines (D0-D2), UDS & LDS (D3 & D4) and the trace from the bridge between the two NOR inputs (D5) (the same signal is present directly on the output of the AND). I know unused inputs should be tied LOW or HIGH but I assume that's when an input isn't used for an individual gate in a quad package?

enter image description here

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    \$\begingroup\$ Show us a schematic of the signals and gates. Also why are you using the 7402 NOR gate? As an inverter? \$\endgroup\$
    – Michael Karas
    Jul 2, 2017 at 23:44
  • \$\begingroup\$ Yeah, as per my comment below (posting here for ease of reading) I'm driving a shift register so I can delay. I had it in my head that I needed to delay highs through that, of course low is fine! \$\endgroup\$
    – Matt Lacey
    Jul 2, 2017 at 23:46

2 Answers 2

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You do not need the NOR gate to detect low on either UDS or LDS or both. The 7408 AND gate can do that in a single gate. 

UDS LDS  OUTPUT
 L   L     L
 L   H     L
 H   L     L
 H   H     H

As you can see you can get a low out of the 7408 when either LDS or UDS are low.

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  • \$\begingroup\$ Oh man, I really was tired last night. Was thinking I needed to invert because it's going into a shift register, but that'll work just fine with that scheme. Jeez. This morning I've just been wondering why the output isn't correct though, like at the start of that sequence, it's seemingly high before either input goes high? \$\endgroup\$
    – Matt Lacey
    Jul 2, 2017 at 23:45
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    \$\begingroup\$ Did you by off chance fall into the age old issue of thinking that the gates of the 7402 type were pinned out the same as the 7408? Gates in 7408 (1 & 2 -> 3; 4 & 5 -> 6; 9 & 10 -> 8; 12 & 13 -> 11). Gates in 7402 (2 | 3 -> 1; 6 | 7 -> 5; 8 | 9 -> 10; 11 | 12 -> 13). If so the downwind 7402 may be playing havoc with your 7408 output. \$\endgroup\$
    – Michael Karas
    Jul 3, 2017 at 3:37
  • \$\begingroup\$ Son of a.... yep. That's exactly what I did! The above issue with the LA frequency was me testing directly on the output of the 7408. I've not used these chips before and (stupidly) assumed the pinout for all quad packages would be the same! \$\endgroup\$
    – Matt Lacey
    Jul 3, 2017 at 4:41
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I'd guess that this is an artifact of your logic analyzer. It's clear that you are only sampling every 250 nsec. I'd guess that the actual signals are rather more complex than you're seeing, and the disconnect between the inputs and outputs is caused by the relatively long propagation delays of your composite circuit. A 7408 has a max propagation delay of 19/27 nsec, while 7402s run 15/22 nsec each, so the worst-case delays are 56/64 nsec. This sort of delay is more than adequate to cause an analyzer fits when the sample rate is so low.

The first thing to do is run your analysis again without the 7402s, and see if you don't get a change. If that doesn't help, try running your analyzer much faster, 20 MHz minimum, and even faster if you can.

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  • \$\begingroup\$ I'm pretty new to this and assumed I was running it fast enough! Just upped it to 24MHz and things are looking MUCH better. I've got a nasty habit of leaving it 20KHz at power up and wondering why everything is out of whack :) \$\endgroup\$
    – Matt Lacey
    Jul 3, 2017 at 2:21

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