I'm putting together a simple DTACK circuit for a 68k homebrew machine, and part of that is requires me to know when either the Upper Data Strobe (UDS) or Lower Data Strobe (LDS) is asserted LOW. I've only got a few random ICs to hand, so I'm attempting to use a 7408 AND and driving the output into two inputs of a 7402 NOR gate.
For some reason the output of the AND gate seemingly isn't correct, it seems to miss pulses and I don't know why. It's a fast chip and I believe we're way within it's tolerances so what should I be looking for?
The output below from my logic analyser shows 3 address lines (D0-D2), UDS & LDS (D3 & D4) and the trace from the bridge between the two NOR inputs (D5) (the same signal is present directly on the output of the AND). I know unused inputs should be tied LOW or HIGH but I assume that's when an input isn't used for an individual gate in a quad package?