I understand as the clock frequency of a chip is increased, some issues arise. Probably, the most known issues are those related to the so-called "power wall", which alludes to the fact the thermal dissipation becomes an issue when the clock reaches a given threshold. However, there is something else I don't get: as the integration scale of the chip (i.e., its density) increases, distances between inner wires (tracks, actually) shortens, increasing capacitances and bounding the clock rate, right? But in which way capacitances inhibit higher frequencies? To quote Stallings:
The speed at which electrons can flow on a chip between transistors is limited by the resistance and capacitance of the metal wires connecting them; specifically, delay increases as the RC product increases. As components on the chip decrease in size, the wire interconnects become thinner, increasing resistance. Also, the wires are closer together, increasing capacitance.
Although I am not an engineer, I can tell why thinner conductors are bad for chips design. But I have no clue why high capacitances may be an issue. May any good Samaritan clarify that for me, please?