# Why unintended capacitances are an issue for the design of chips?

I understand as the clock frequency of a chip is increased, some issues arise. Probably, the most known issues are those related to the so-called "power wall", which alludes to the fact the thermal dissipation becomes an issue when the clock reaches a given threshold. However, there is something else I don't get: as the integration scale of the chip (i.e., its density) increases, distances between inner wires (tracks, actually) shortens, increasing capacitances and bounding the clock rate, right? But in which way capacitances inhibit higher frequencies? To quote Stallings:

The speed at which electrons can flow on a chip between transistors is limited by the resistance and capacitance of the metal wires connecting them; specifically, delay increases as the RC product increases. As components on the chip decrease in size, the wire interconnects become thinner, increasing resistance. Also, the wires are closer together, increasing capacitance.

Although I am not an engineer, I can tell why thinner conductors are bad for chips design. But I have no clue why high capacitances may be an issue. May any good Samaritan clarify that for me, please?

Higher capacitance inside the IC has several effects, among them:

1) Signal degradation. A sharp pulse going thru an RC filter will go out "less sharp". Namely, it if had a fast rise-time at the input of the RC, at its output the rise time will be slower. If it is slower, it may grow not fast enough so that the receiving end recognizes a change from '0' to '1' or viceversa in time (*)(a conductor between a transmitter and a receiver can be modeled as a series resistance and a parallel capacitor in the termination, thus the R-C).

2) Crosstalk. Capacitance between conductors is one of the causes of crosstalk. Crosstalk means that the data changing in one conductor affects the data on a neighbor conductor. This can corrupt the data or at least worsen its signal to noise ratio.

(*) Digital circuits change all the time with fast clocks. If a signal gets slowed down because capacitance in the conductor, it may not change fast enough for the receiver and the next clock pulse may sample a wrong value of the 'slowed down' signal.

Key formula for energy consumption:

$$SignalPower = Frequency * Capacitance * Voltage * Voltage$$

Finer resolution permits smaller FETs, thus the baseline FET will have less output current.

Finer resolution permits smaller FETS, which being smaller in all dimensions does require a shorter time for electrons to cross from Source to Drain; this produces faster propagation delay and permits faster clock rates.

Finer resolution permits tighter packing of metallization, raising the sidewall capacitances of MCU busses (those 16 wide or 32 wide data highways).

Thus we have a TRIPLE hit: more capacity, higher MCU clock frequency, but weaker transistors.

• And how is this an answer to the question from the OP? – Claudio Avi Chami Jul 4 '17 at 4:06