I need help in understanding the solution from solution manual. The question is from the exercise 4.22.2 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition). The question is about branching in instruction pipeline.
The question
We assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor. Consider the instruction sequence:
Label1: LW R2,0(R2)
BEQ R2,R0,Label ; Taken once, then not taken
OR R2,R2,R3
SW R2,0(R5)
Draw the pipeline execution diagram for this code, assuming there are delay slots and that branches execute in the EX stage.
The solution given is as follows:
Doubts
- Why there is a stall (highlighted
***
) in cycle 7 forLW
(4th executed instruction)? I understand thatLW
readsR2
which is modified byOR
( executed in delay slot afterBEQ
, beforeLW
). ButOR
reads it in cycle 6 in theEX
stage. SoLW
should be able to executeEX
stage in cycle 7 (since full forwarding is allowed). But why its not shown like that? - Also notice that in cycle (column) 4, for
BEQ
instruction (2nd instruction), their is a stall (i.e.***
). This is becauseBEQ
readsR2
which is loaded byLW
(1 st instruction) in itsMEM
stage. SoBEQ
has to wait tillLW
'sMEM
completes. However the same situation occurs in instructions 4 and 5. But in this caseBEQ
(5th instruction) is allowed to execute itsEX
stage in the same cycle asLW
's (3rd instruction's)MEM
stage. Shouldn'tBEQ
(5th instruction) be stalled again to make it wait tillLW
's (4th instruction's)MEW
completes? - Also I noticed, there are two 4th stages. In some instructions, 4th stage is labeled
MEM
(for example 1st instructionLW
, 4th cycle) and in some instructions, its labeledMEB
(for example 2nd instructionLW
, 6th cycle). What are the differences betweenMEM
andMEB
? I searched whole book, but their is no mention ofMEB
, only in solution manual, its specified. Or may be I might have missed some pages.