I need help in understanding the solution from solution manual. The question is from the exercise 4.22.2 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition). The question is about branching in instruction pipeline.
We assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor. Consider the instruction sequence:
Label1: LW R2,0(R2)
BEQ R2,R0,Label ; Taken once, then not taken
Draw the pipeline execution diagram for this code, assuming there are delay slots and that branches execute in the EX stage.
The solution given is as follows:
- Why there is a stall (highlighted
***) in cycle 7 for
LW(4th executed instruction)? I understand that
R2which is modified by
OR( executed in delay slot after
ORreads it in cycle 6 in the
LWshould be able to execute
EXstage in cycle 7 (since full forwarding is allowed). But why its not shown like that?
- Also notice that in cycle (column) 4, for
BEQinstruction (2nd instruction), their is a stall (i.e.
***). This is because
R2which is loaded by
LW(1 st instruction) in its
BEQhas to wait till
MEMcompletes. However the same situation occurs in instructions 4 and 5. But in this case
BEQ(5th instruction) is allowed to execute its
EXstage in the same cycle as
LW's (3rd instruction's)
BEQ(5th instruction) be stalled again to make it wait till
LW's (4th instruction's)
- Also I noticed, there are two 4th stages. In some instructions, 4th stage is labeled
MEM(for example 1st instruction
LW, 4th cycle) and in some instructions, its labeled
MEB(for example 2nd instruction
LW, 6th cycle). What are the differences between
MEB? I searched whole book, but their is no mention of
MEB, only in solution manual, its specified. Or may be I might have missed some pages.