I am designing a board to drive a DC micromotor which requires a 100kHz PWM signal. The board is mainly a digital design board, with very little analog signalling. I am planning on driving the motor with the STSPIN240 motor IC via an STM32 MCU. The supply voltage is 6V, I need a motor voltage of 4V98, i.e. drive the motor at 100kHz PWM at a duty cycle of 0.83 for the desired torque/speed characteristics at max load.

The signal tracking from the MCU to the motor IC will travel approximately 70mm. The motor IC PWM output goes to a daughter board via two male/female kk connectors + cable. It then goes from the bottom to the top of the board, ~30mm tracking, and comes off this daughter board via two male/female kk connectors + cable to the DC motor.

The board is a four-layer board. Signal, signal ground, power, signal. The steps I plan on taking for these signals:

  1. MCU PWM signals will be given dedicated tracks, will not use vias and will go as direct as possible.
  2. The ground plane in the PCB will provide the path for the the MCU PWM path.
  3. Any time a PWM signal crosses a signal it will cross it perpendicularly.
  4. The MCU output and input will be tracked directly to the connector (distance of <10mm)
  5. The MCU PWM output cables will be twisted, length of 30mm.
  6. The tracks on the daughter board will be tracked and via'd to the top layer for the second connector with <30mm of tracking.
  7. The cable to the motor IC is a ribbon cable, should this made into another twisted pair?
  8. When the signal goes to a connector the connector will be surrounded by via's to ground.

Do these layout considerations sound sufficient?


The analog signals will be trashed, if there is strong coupling via electrostatic fields and the analog node impedance (not resistance but impedance) is HIGH. The coupling is by high-pass-filter; any resistance on the analog signal is sufficient to implement a DC_response.

Consider capacitive coupling, of 1mm by 1mm overlap of your perpendicular traces, with 1/3 of 1/16" spacing (0.5mm). Er of FR4 is 5. The capacitance is

Eo * Er * Area/Distance = 9e-12 * 5 * 1mm * 1mm 0.5mm = 9e-11 * 1mm = 9e-14 farad. Or ~~ 1e-13 Farad

If your node has 10pF capacitance, your injected voltage level is 1% of the PWM signal (plus any switching spikes).


Regarding magnetic fields, I use

Vinduce = 2e-7 * Area/Distance * dI/dT

where Area is the length * width of a vulnerable analog signal/RTN loop and Distance is the closest spacing between PWM lines and that analog loop.

Assuming 1cm loop (0.01 meter * 0.01 meter) at 1cm distance, the PWM switching 1amp in 100 nanoseconds, the Vinduce is

2e-7 * 0.01 * 0.01 / 0.01 * 10^7 amp/second

2e-7 * 0.01 * 10^7 = 0.02 volts

At 100 nanosecond switching edge, any planes will have a few dB of Skin Effect shielding. Slower edges will be even less attenuated, but also will induce smaller voltages into the analog loop.

  • \$\begingroup\$ The PWM signal may not be 1 Amp, I read that as a signal from the controller not the power electronics driver. Also wouldn't the signal ground and power planes be sufficient to isolate the perpendicular traces from capacitive coupling? \$\endgroup\$ May 25 '20 at 4:15

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