# pulse response of opamp integrator

I was simulating the below opamp integrator circuit with pulse current.As this is an inverting integrator I thought it would integrate the input current and give me a triangular waveform. But after simulation in PSpice I got the following result.

Can anyone explain why the current flowing through capacitor jumping to 0 to 2u instead -1u to 1u. Also why Vout is almost constant at 15v.

From my understanding, if dc current flows through capacitor then the voltage across through capacitor will be ramp. • It might be the initial conditions that are wrong. – Andy aka Jul 5 '17 at 14:37
• Thanks a lot....From last two hours I am trying to figure out this weird behavior. Now I just added IC=0 in capacitor....I am getting triangular waveform. – new_ecl Jul 5 '17 at 14:48

Assuming this was an ideal op amp your question is answered by the initial condition at time zero for your simulation. If the current in the capacitor was zero at time zero, and the voltage at the output was zero at time zero, the current and voltage waveforms would be as you describe.

Since this is in the real world, and the initial conditions are I = -1u, the op amp starts out saturated because C1 is charged to a large negative voltage.

To get the desired result, simulate a switch across C1 with the switch closed, and open the switch a short time after your current starts. If you vary the start time delay, the triangle wave will have a differing DC component.

• why C1 is charged to large negative value? Can you please explain..? – new_ecl Jul 5 '17 at 16:49
• John I am trying to solve ibb.co/caAH9a this question....can you comment what is the difference between these two scenarios....I am not getting....When I=-1uA at t=0..capacitor will be fully discharged but...if I=0 at t=0 then it is Vout=0 so capacitior will be in its initial stage. – new_ecl Jul 5 '17 at 17:13
• If I = -1u for time before t0, then the current must come from the capacitor. The capacitor side connected to the negative op amp input will be pulled down and the output of the integrator will rise until it hits +15 V. The op amp side of the capacitor will continue to be charged more negatively until it gets to the compliance voltage of the current source. – John Birckhead Jul 5 '17 at 17:14
• Sorry last comment was before I got your question. One way of looking at it is this: 1. The negative input of the op amp must be at 0 (virtual ground). If it is not, the op amp, which has nearly infinite open-loop gain, is in saturation. 2. there is (virtually) no current flowing into the op amp input, so the resistor current must equal the capacitor current. The resistor current is -1ua, so the capacitor current has to be 1ua. Since I(capacitor) = C*dv/dt, and C = 1uf the dv/dt must be 1ua/1uF or 1 volt per second. WHen you have -1ua on the input the slope of the voltage is 1 v per sec – John Birckhead Jul 5 '17 at 17:18
• I understood why C1 will be charged to a large -ve value....But what will happen when I=0 at t=0...can I expect a triangular response.? Can you tell me how the output voltage will look in these two different scenarios? – new_ecl Jul 5 '17 at 17:19

It might be the initial conditions that are wrong.

Thanks a lot....From last two hours I am trying to figure out this weird behavior. Now I just added IC=0 in capacitor....I am getting triangular waveform.