For my graduation work I am developing a microcontroller system where the MCU (MSP430FR5739) talks to an SPI flash (SST25VF080B to be particular). I've achieved this without using the eUSCI SPI master (by bit-banging the thing) but no matter what, the flash always returns a 0x00 byte if I don't leave gigantic 2000-cycle delays between clock pulses.

On the datasheet it says that the flash could work at up to 80 MHz, and I've clocked the MSP430 at 24 MHz, so my thought process here is that it should be working without any delays at all.

My questions would be:

  1. The flash IC is on a daughterboard and is connected to the main board with approximately 2 inches of 22 AWG single core wire. I know that solid core wire is terrible for high frequency, but would replacing these help speed it up?
  2. If I most certainly have to have the delays, what else can I do to speed it up?
  • 2
    \$\begingroup\$ How many microseconds is a 2,000-cycle delay? Do you mean 83us (2,000/24MHz)? How long after powering on the device do you start trying to talk to it? Do you have good bypass caps on the part? \$\endgroup\$ – supercat May 8 '12 at 20:27
  • 3
    \$\begingroup\$ Another thought: does your clock idle high or low, and how well connected is your VDD? If the clock idles high, and you have bypass caps but no actual VDD connection, it could be that the protection diodes are kinda-sorta powering the device, provided there's enough idle time to recharge the bypass cap between bits. \$\endgroup\$ – supercat May 8 '12 at 20:30
  • 2
    \$\begingroup\$ If there aren't any bypass caps near the flash chip, that could be a problem. It may be that one clock pulse in isolation won't glitch VDD quite enough to confuse the chip, but sending repeated pulses, without letting VDD stabilize between them, would. If a device both (1) holds internal state, and (2) is designed to operate at high speeds, it should not be expected to work at all usefully without dedicated bypass caps placed very close to it. Don't bother worrying about anything else until that problem is fixed. \$\endgroup\$ – supercat May 8 '12 at 20:58
  • 1
    \$\begingroup\$ Thanks @supercat, I added a 100nf cap right next to the VDD pin of the flash IC and now it works without any delays. Never would've thought bypass caps were this important. \$\endgroup\$ – özg May 10 '12 at 10:32
  • 1
    \$\begingroup\$ Glad to be of help. My comment wasn't as precise as it could have been; basically, I would recommend that one assume that if a device doesn't have proper bypass caps, all internal and external state may be arbitrarily glitched (or not) any time an input or internal state changes. If the nature and usage of a device is such that this won't matter, one might get by without bypass caps. Otherwise, they're so essential that it's not worth spending any time troubleshooting circuits which don't have them, since few problems could occur that could be shown to have any other cause. \$\endgroup\$ – supercat May 13 '12 at 20:06

What concerns me is your disregard for EMC issues in your design when it uses 2" of 24AWG wire for signal wiring without mentioning any ground planes.

A systematic approach must be considered in communication of all signals to determine, which need shielding, common mode filter, ground plane, star ground, radial ground and impedance control on high speed signals.

Can you obtain some low capacitance FET probes or better yet, Tektronix differential FET Probes and scope the clock & data signals at both ends?

Also remember the specs only say 80MHz is MAX and THERE IS NO MIN. Also Maximum clock frequency for Read Instruction, 03H, is 33 MHz in the fine print for this 80MHz part. (darn those marketing guys)

THings to do to improve performance;

  1. Use AWG30 twisted pair 12 turns/ft for every signal to this chip where you need better shielding and less overshoot ripple.
  2. Have a dedicated regulator @ Vdd @ 3.6V for both IC's. Notice there is no spec for the 80MHz part yet the 66MHz part says VDD = 3.0 - 3.6 V, CL = 15 pF, so I would use Vmax=3.6 to get as much performance as possible. (darn those ambiguous specs)
  3. Verify all voltage levels, rise times and setup times.
  • \$\begingroup\$ No fine print, the "Read (25/33 MHz)" is even a section heading (p.10). The next page shows a high speed read function which works at 80MHz. \$\endgroup\$ – stevenvh May 13 '12 at 13:20

Most of these parts have separate commands for low (<25Mhz) and high speed reads. When using the high speed read you typically must send one or more dummy characters before the part starts clocking out data. Once it's clocking data you should receive one byte of data for every 8 clock pulses.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.