# CMOS Inverter DC charecteristics steepness

I was trying to solve the following multiple choice question(only one option is correct).

I simulated the inverter for varying W with L constant. What I found is the absolute value of dVout/dVin increases when W decreases.

Can anyone explain this? I went through this question where I found the small signal gain increases with decreasing W. But here we are looking at large signal behavior. Also please mention the solution of the above question.

• And the source of the information that you quote is? I ask this because (c) and (d) are opposing each other and this looks like nonsense to me. – Andy aka Jul 7 '17 at 11:54
• only one option is correct...This is a multiple choice question. – new_ecl Jul 7 '17 at 13:17
• Ah you've edited the question! – Andy aka Jul 7 '17 at 13:19

The question is not very well formulated and this is the main problem here. However, the most likely answer is (d).

Generally the transition slope can be described by the small signal gain $A_V$ of the circuit which is given by $$A_V = -\frac{g_{m,p} + g_{m,n}}{g_{ds,p} + g_{ds,n}}$$ where $g_{m,p}$ and $g_{m,n}$ are the transconductances and $g_{ds,p}$ and $g_{ds,n}$ the output conductances of the PMOS and NMOS transistors, respectively.

So, the sum of transconductances needs to be maximized and the sum of the conductances minimized.

Using $$g_m = \frac {2 I_D}{V_{GS}-V_T}$$ where $I_D$ is the drain current, $V_{GS}$ the gate-source voltage and $V_T$ the threshold voltage of the transistor. For the output conductane we can write $$g_{ds} = \lambda^\prime / L \cdot I_D$$ where $\lambda^\prime$ is a constant and L the transistor's channel length.

Now an important observation can be made. Using these two expressions in the equation for the gain $A_V$ the current ID drops out of the equation, since both gm and gds are proportional to the current and only their ratio determines the gain.

Making the assumption that the switching threshold of the inverter is at half the supply voltage it can be shown that (d) is the correct answer. Since the gate-source voltage of both transistors is half the supply voltage the expression for gm is $$g_m = \frac{2 I_D}{V_{GS}-V_T} = \frac{2 I_D}{V_{DD}/2-V_T}$$ with $V_{DD}$ being the supply voltage. As shown above, the drain current drops out of the equation, so the contribution of transconductance is constant. Therefore the only way to increase the gain AV is by decreasing gds. With $g_{ds} = \lambda^\prime / L \cdot I_D$ and noting that $I_D$ gets cancelled when used in the expression for $A_V$, an increase of L will result in a decrease of gds and therefore will result in a higher gain.

However, if the switching threshold is not centered things are different. We can maximize the transconductance of either the PMOS or the NMOS transistor and get a steeper slope. To move the switching threshold the width of the PMOS or the NMOS could be increased. This would result in (a) or (b) as the correct answer.

This could also explain the results you got from simulation, if you didn't properly adjust the switching threshold of the inverter before and after changing the width.

• I adjusted the switching threshold and kept it in the middle. – new_ecl Jul 7 '17 at 19:13