# Strange Voltage Levels in a Multi-slave Full-duplex rs485 bus

I am working on a project using rs485 bus for communication. Here are design parameters:

• Bus can include 1 master and 30 slaves
• Configuration is full duplex using 4 wires.
• All slaves attached to SLAVE(Y-Z) -> MASTER(A-B) for transmitting
• All slaves attached to SLAVE(A-B) -> MASTER(Y-Z) for receiving
• Master is always listening. (Receive Enabled)
• Master is always driving. (Drive Enabled)
• Slaves are always listening. (Receive Enabled)
• Slaves are always NOT driving. Except when they want to send data then drive enable. According to the datasheet, When not drive enable, the outputs are high-impedance.
• Master and all slaves are using max491.
• There is a single 12V power source. Every slave and master is connected to this power source as parallel to each other and has their own step down converters to produce needed voltages. Thus all system share a common ground.
• I tried failsafe biasing on master side and it worked. With failsafe biasing 4 slaves and 1 master communication is working fine. (but question is about 20 slaves biasing calculation)

OBSERVATION

These plots are excel plots simplified from actual scope measurements

When the system is made up with 1 slave and 1 master, voltages on Slave Y-Z bus (slave transmit bus) are like this:

Thus communication happens successfully.

When the system is made up with 2 slaves and 1 master, voltages on Slave Y-Z bus (slave transmit bus) are like this:

This way, communication happens successfully. As we see there is a change in voltage levels. Comm happens because voltages are still on the correct sides of middle senseless zone (which is +-0.2v from the center)

When the system is made up with 3 slaves and 1 master, voltages on Slave Y-Z bus (slave transmit bus) are like this:

This way, as you can see, no communication happens because voltages are on the wrong side of the senseless zone. And levels are strange (to me).

Going further analysis, I made 4 slaves and 1 master config. Here is the result:

Voltages go up a little bit more.

The voltage difference between Y and Z line in each config shows the max491 has some serious impedance on the line when in high-impedance mode.

I bought these max491 chips from a local dealer then checked the price from digikey. What I saw is my prices are 3 times lower than digikey prices for the chip. Maybe the chips are clones. I don't know. But I have to use them.

QUESTION

The question is how can I calculate this "parasitic" impedance and build a biasing circuit for this and what may be the reason? I am a little bit confused. I am going to build 20 slave and 1 master configuration and I cannot imagine what the voltages are going to be.

NOTES

• There is no problem on slave receiving bus
• This observations are nearly the same when master side termination resistor used.
• There is no possibility of 2 or more slaves transmitting at the same time. There is a hardware sync built in. This is tested.

Edit

The schematic is like that. Nothing more. Average cable length between slaves is 1.5 meters. Cable is CAT6 - UTP8. For transmit and receive, twisted pairs are used.

• Slave data sheet maybe? – Andy aka Jul 7 '17 at 18:00
• Slaves are also using the max491. Mcu is atmega328. – Mert Gülsoy Jul 7 '17 at 18:30
• Where's the schematic? – CL. Jul 7 '17 at 18:40
• Will be added. :) – Mert Gülsoy Jul 7 '17 at 18:59
• @MertGülsoy "The schematic is like that. Nothing more." If that schematic is complete, then a common ground between the devices is missing. The likely effect of that missing reference is difficult to guess, without lots more detail about the master/slave devices and their power sources (I notice that you have not given details about power sources - is that secret or can you give more info?). Or you could analyse how best to add the common ground and try it. Or did you perform tests and decide that a common ground connection is not required? If so, please share that test setup and its results. – SamGibson Jul 7 '17 at 22:16

It looks to me like your DE lines on the slaves are being driven wrong. Your bus voltages are (qualitatively) what I'd expect if the "unselected" slaves are in fact being driven active with a high input to each "unselected" slave DI.

As the number of slaves increase, the total bus drive from the unselected units increases, and the selected output has less and less effect on the bus voltage.

The obvious check would be to get the effects you've shown, then pull the selected slave chip from the circuit, and look at bus voltage. If the other chips are inactive, the bus differential voltage should drop to more or less zero.

Heh. Or, of course, the reason that your chips cost 1/3 the Digikey rate might be that they don't work properly, and the DE line has no effect. Just sayin'.

• Seems like DE lines just cut the high side. Low side is still connected (Not high-impedance) because changing voltages are low side on non-inverting output and high side on inverting output. – Mert Gülsoy Jul 8 '17 at 12:39
• @MertGülsoy - That is both irrelevant and wrong. Effectively, each output will either connect to ground, +5, or make no connection, depending on circuit status. But it doesn't matter. Do as I said. Set up the circuit as you have shown, then pull the selected slave (the one you think is selected). Make sure power is applied to all slaves. Does the bus differential voltage go to zero? If not, you have enable problems. – WhatRoughBeast Jul 8 '17 at 13:59
• I will try and write here the result. – Mert Gülsoy Jul 8 '17 at 14:57
• After through inspection here with the given answers I think that this answer is acceptable because I came to same conclusions. Thank you. – Mert Gülsoy Jul 21 '17 at 8:49

First, to clear up terminology, the topology that you describe is RS-422 since RS-485 is a two wire, half duplex scheme. I have had thousands of large RS-422 networks deployed without the problems you are experiencing.

Check that you are using the correct transmit enable logic. It is opposite of the receive enable logic. Put a scope or high speed logic probe on each one to confirm its state and that it has no transients.

The devices you have chosen are not slew rate limited so cable impedance, cable capacitance, reflections, terminations, and cross talk become more critical concerns. You should run a single change elimination experiment for each of these factors.

Slowing down your baud rate dramatically may give you more clues as to the cause of your problem.

Your method of plotting bus voltages could be part of the problem if it does not employ high impedance differential sensors.

You specifically mentioned that the conditions are the same when master side termination is used. Depending on the distribution topology and clock speed, you may find it necessary to place terminations on both ends of the cable. Make sure you have pure resistive terminations - not all film resistors are.

If none of this resolves the problem, post your schematic, cable specifications, termination value(s) and location(s), and pictures of your test setup to allow further insights. You should also comment on how you took your bus measurements since the plots are obviously very low bandwidth and therefore missing important details. And don't forget to include a proper X axis scale with any such plots.