I am working on a project using rs485 bus for communication. Here are design parameters:
- Bus can include 1 master and 30 slaves
- Configuration is full duplex using 4 wires.
- All slaves attached to
SLAVE(Y-Z) -> MASTER(A-B)for transmitting
- All slaves attached to
SLAVE(A-B) -> MASTER(Y-Z)for receiving
- Master is always listening. (Receive Enabled)
- Master is always driving. (Drive Enabled)
- Slaves are always listening. (Receive Enabled)
- Slaves are always NOT driving. Except when they want to send data then drive enable. According to the datasheet, When not drive enable, the outputs are high-impedance.
- Master and all slaves are using max491.
- There is a single 12V power source. Every slave and master is connected to this power source as parallel to each other and has their own step down converters to produce needed voltages. Thus all system share a common ground.
- I tried failsafe biasing on master side and it worked. With failsafe biasing 4 slaves and 1 master communication is working fine. (but question is about 20 slaves biasing calculation)
These plots are excel plots simplified from actual scope measurements
When the system is made up with 1 slave and 1 master, voltages on Slave Y-Z bus (slave transmit bus) are like this:
Thus communication happens successfully.
When the system is made up with 2 slaves and 1 master, voltages on Slave Y-Z bus (slave transmit bus) are like this:
This way, communication happens successfully. As we see there is a change in voltage levels. Comm happens because voltages are still on the correct sides of middle senseless zone (which is +-0.2v from the center)
When the system is made up with 3 slaves and 1 master, voltages on Slave Y-Z bus (slave transmit bus) are like this:
This way, as you can see, no communication happens because voltages are on the wrong side of the senseless zone. And levels are strange (to me).
Going further analysis, I made 4 slaves and 1 master config. Here is the result:
Voltages go up a little bit more.
The voltage difference between Y and Z line in each config shows the max491 has some serious impedance on the line when in high-impedance mode.
I bought these max491 chips from a local dealer then checked the price from digikey. What I saw is my prices are 3 times lower than digikey prices for the chip. Maybe the chips are clones. I don't know. But I have to use them.
The question is how can I calculate this "parasitic" impedance and build a biasing circuit for this and what may be the reason? I am a little bit confused. I am going to build 20 slave and 1 master configuration and I cannot imagine what the voltages are going to be.
- There is no problem on slave receiving bus
- This observations are nearly the same when master side termination resistor used.
- There is no possibility of 2 or more slaves transmitting at the same time. There is a hardware sync built in. This is tested.