DDR4 reportedly uses something called pseudo-open-drain-logic or PODL. How does it work?
Perhaps I can add a little simple information. As I understand it, POD (Pseudo Open Drain) drivers, have a strong pulldown strength but a weak pullup strength. A pure open-drain driver, by comparison, has no pullup strength except for leakage current; this is why the term "pseudo" is used. The remaining pullup strength is provided by parallel-terminating the receiver at the far end to the HIGH voltage, often using a switchable, on-die terminator instead of a separate resistor. The purpose of all this is to reduce the overall power demand compared to using both strong pullup and strong pulldown, as in drivers such as HSTL. DDR4 memory uses POD drivers, replacing push-pull drivers in DDR3 that drove strongly in both High and Low states.
You can get the standard from JEDEC (Free, registration required). It has single-ended master driving address and command bits. Each slave has a pull-up to VDDQ such that the parallel resistance is 60 ohms.
PSEUDO OPEN DRAIN (POD)
The output device is a MOSFET the output is called open drain and it functions in a similar way to "open collector" transistor switches. When open it appears like a charged capacitor & discharged when closed. So the memory state is sensed by voltage and not current.
EDA360.... DDR4 SDRAMs will not use stub-series terminated logic drivers. Instead, they’ll use pseudo-open drain (POD) drivers with Vdd terminations. Because of higher density defects, they’ll use data-bit inversion (DBI), on-chip parity detection for the command/address bus, and CRC error detection for the data. Mux'ing these chips on board gets more complex so they are developing new stds such as load-reduced DIMMs (LRDIMMs) which maintains currency latency 8ns if it works, but 2x throughput.
Wiki clip.. In January 2011, Samsung completed development of what it claimed was the industry's first DDR4 DRAM module using a process technology with a size between 30 nm and 39 nm. The module could reportedly achieve data transfer rates of 2.133 Gbit/s at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30 nm-class process technology with speeds of up to 1.6 Gbit/s. The module used pseudo open drain (POD) technology, specially adapted to allow DDR4 DRAM to consume just half the current of DDR3 when reading and writing data.
EDA360.... DDR4 SDRAMs will have double the maximum capacity of DDR3 SDRAMs. They’ll also have twice the maximum clock frequency. Like DDR3 SDRAMs, DDR4 SDRAMs will have an 8n prefetch (important for cache-line-filling operations) but a DDR4 memory controller must alternate or rotate between SDRAM bank groups for maximum SDRAM performance. That’s a new restriction.
Actual design details are proprietary and my opinions are hypothetical. Tony
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Last minute details
Now the DBI reduces the cross-talk of all these symbols being stuck at 0 or 1, so an extra bit can choose to invert the data when set to 1, like an odd parity or RLL encoding scheme to reduce ISI from consecutive all ones or zeros.
What's this stuff about PSEUDO? (I need Bob Pease to explain this in part 2... Bob are you reading this?)
The Pseudo hasn't changed too much, nor the POD concept, but the stuff to make it work at these speeds and size has made it more complex. There is another compatibility downside, it needs to run above a certain speed to work. Parity is no longer an option and is used on Addresses and CRC is used on data.
I forgot to mention DDR4 will actively queue memory fetches on a priority basis to improve performance. So SDRAM's are much more than just POD memory chips.
DDR5 will mux memory even more and faster... can't wait... (written 2012, now due 2020)
DDR6 later can't wait