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I am trying to perform a software reset of my STM32F2. (Reference manual available here.) The relevant page of the reference manual (page 80) gives little information. Basically, the SYSRESETREQ bit of the Application Interrupt and Reset Control Register must be set.

Now this page explains that to be able to modify the SYSRESETREQ, a specific "key" needs to be written to the VECTKEY bits.

Neither document explains where this Application Interrupt and Reset Control Register is. What is its address, and how can I access it?

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Why don't you use the CMSIS library? There is a specific function for that.

Moreover, This is the Code taken from CMSIS Library for System Software Reset:

/******************************************************************************
 * @file:    core_cm3.h
 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
 * @version: V1.20
 * @date:    22. May 2009
 *----------------------------------------------------------------------------
 *
 * Copyright (C) 2009 ARM Limited. All rights reserved.
 *
 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
 * processor based microcontrollers.  This file can be freely distributed 
 * within development tools that are supporting such ARM based processors. 
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ******************************************************************************/

/* memory mapping struct for System Control Block */
typedef struct
{
  __I  uint32_t CPUID;                        /*!< CPU ID Base Register                                     */
  __IO uint32_t ICSR;                         /*!< Interrupt Control State Register                         */
  __IO uint32_t VTOR;                         /*!< Vector Table Offset Register                             */
  __IO uint32_t AIRCR;                        /*!< Application Interrupt / Reset Control Register           */
  __IO uint32_t SCR;                          /*!< System Control Register                                  */
  __IO uint32_t CCR;                          /*!< Configuration Control Register                           */
  __IO uint8_t  SHP[12];                      /*!< System Handlers Priority Registers (4-7, 8-11, 12-15)    */
  __IO uint32_t SHCSR;                        /*!< System Handler Control and State Register                */
  __IO uint32_t CFSR;                         /*!< Configurable Fault Status Register                       */
  __IO uint32_t HFSR;                         /*!< Hard Fault Status Register                                       */
  __IO uint32_t DFSR;                         /*!< Debug Fault Status Register                                          */
  __IO uint32_t MMFAR;                        /*!< Mem Manage Address Register                                  */
  __IO uint32_t BFAR;                         /*!< Bus Fault Address Register                                   */
  __IO uint32_t AFSR;                         /*!< Auxiliary Fault Status Register                              */
  __I  uint32_t PFR[2];                       /*!< Processor Feature Register                               */
  __I  uint32_t DFR;                          /*!< Debug Feature Register                                   */
  __I  uint32_t ADR;                          /*!< Auxiliary Feature Register                               */
  __I  uint32_t MMFR[4];                      /*!< Memory Model Feature Register                            */
  __I  uint32_t ISAR[5];                      /*!< ISA Feature Register                                     */
} SCB_Type;

#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address    */
#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address    */
#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct             */

#define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access   */
#define NVIC_SYSRESETREQ            2         /*!< System Reset Request         */

/* ##################################    Reset function  ############################################ */
/**
 * @brief  Initiate a system reset request.
 *
 * @param   none
 * @return  none
 *
 * Initialize a system reset request to reset the MCU
 */
static __INLINE void NVIC_SystemReset(void)
{
  SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
  __DSB();                                                                                 /* Ensure completion of memory access */              
  while(1);                                                                                /* wait until reset */
}
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You aren't finding enough information because you're looking in a wrong place. NVIC is a part of the core and as such is documented in the ARM literature.

ARMv7-M ARM section B1.5.16 details the two reset methods available in the Cortex-M3 core, local and system reset. Memory addresses of system control registers including AIRCR can be found in section B3.2.2 (table B3-4). The AIRCR itself is documented in section B3.2.6. This is where you can find the exact value for the key than you need to unlock the reset feature.

However, as Katte has noted, CMSIS contains both a dedicated function to do the reset and macro definitions for all register addresses and values required. You should become familiar with it as its source code often contains information hard to find anywhere else (except manuals, of course).

The Definitive Guide to the ARM Cortex-M3 section 14.4 documents all this in a lot of detail. If you don't have it you can try using Google Books to read it (and hope that pages you need won't be omitted).

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In case someone still looking for an answer to this question, my solution would be a bit different by using the WatchDog module of the CPU to reset the device.

Quick tip - if the downcounter is reloaded outside the window it will trigger a reset (so the reset can be almost instant).

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