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Assuming i have these two codes:

module wire_example( a, b, y);
  input a, b;
  output y;

  wire a, b, y;

  assign y = a & b;

endmodule

and the second one is:

module reg_combo_example( a, b, y);
input a, b;
output y;

reg   y;
wire a, b;

always @ ( a or b)
begin   
  y = a & b;
end

endmodule

my question is what is the difference in the net list, both of them will have an gate, but will the module with reg y will have a flip flop or a latch to hold the data while wire y won't have any latch?

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2 Answers 2

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Neither of your examples will contain any latches or flip-flops. The always block in your second example is combinational, not sequential (if it were to synthesize a latch, what clock would control that latch?). You have to use a reg type for y simply because it appears on the left side of an assignment statement inside an always block. Many people consider this a disadvantage of Verilog, which is hard to argue with. In VHDL, a signal type would be used instead of both wire and reg, removing the confusion.

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  • 5
    \$\begingroup\$ .... which is why you use SystemVerilog and just declare a "logic" \$\endgroup\$ Commented Jun 30, 2012 at 4:57
  • \$\begingroup\$ will using a reg instead of wire result in slower circuit? \$\endgroup\$
    – Mah35h
    Commented Dec 26, 2021 at 6:20
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wire:

It is a net which represents the connections between components. It is used for continuous assignments, that is, wire has its value continuously driven on it by outputs of the devices connected to them.

reg:

It is used for procedural assignments. reg always doesn’t mean a flop/register. reg can also keep its value until another value is placed into the registers.

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