# Little change in Verilog module results in high change in power consumption (Synopsys Design Compiler)

I am comparing two Verilog designs:

• Design (1): A top module that is driven by a clock running at 50MHz, which is the main system clock.

• Design (2): The same top module as in Design (1) with one difference, i.e., the main system clock runs at 400MHz, but I use a divide-by-8 (/8) clock divider to obtain the same clock frequency as Design (1).

Intuitively, the two designs should have comparable power consumptions. The primary reason behind this intuition is that the two top modules of the two designs are running at the same clock frequency of 50MHz. However, it is expected that Design (2) consumes slightly more power, due to using the overhead clock divider.

However, after synthesizing the two designs using Synopsys Design Compiler, the power reports of the two designs indicate that Design (1) consumes 63.4 micro Watts, whereas Design (2) consumes 500 micro Watts, i.e., Design (2) consumes almost 8X the power consumed by Design (1). Please note that the reported power figures refer to the total power consumption, i.e., the sum of all power categories.

In an effort to understand the reason behind this 8X higher power, I suspected that the /8 clock divider is responsible. However, after synthesizing the divider alone (all by itself) with a master clock frequency of 400MHz, its total power consumption turns out to be 35.4 micro Watts only. The numbers don't seem to add up somehow, no?

Anyway, I hope someone can explain to me the source of this 8X higher power, please? Thanks in advance.

PS: I guess the question does not need my Verilog sources and synthesis scripts, right? Regardless, please let me know if these are needed, and I will update the question with more details.

I have seen that some synthesizers are intelligent enough to optimize logic expressions.

If the source code for example contains:

(A or B) and (A or C)


... they will actually produce the following logic on the FPGA:

A or (B and C)


If your synthesizer did so it may happen that not only the /8 divider will "see" the 400 MHz signal.

A hypothetical example:

B might be a 400 MHz input signal and C might be another signal which behaves in a way that the expression B and C might result in a 50 MHz signal. The duty cycle of B and C would not be 50% in this case but the duty cycle is not that important for the power consumption of CMOS circuits.

If you have the following code (here pseudo-code, not Verilog):

Z = B and C
Y1 = X1 or Z
Y2 = X2 or Z
...
Y100 = X100 or Z


... you might think that only one logic cell receives a 400 MHz signal: The one that generates the signal Z.

However the optimizer might optimize the logic the following way:

Y1 = X1 or (B and C)
Y2 = X2 or (B and C)
...
Y100 = X100 or (B and C)


... which means that all logic cells are driven with 400 MHz.

For many FPGA types the power consumption of a cell mainly depends on the fastest input signal of that cell while the other input signals have less impact on the power consumption.

Please also note that some FPGAs have "global clock lines" which are inputs to all logic cells used (maybe even if the signal is unused). Feeding a high-frequency signal into such a line would be a bad idea.

• Sorry, but I couldn't see how some logic optimizations may lead to increase in power consumption. Is it possible to give an example? – user84204884834329 Jul 9 '17 at 19:45
• @user84204884834329 I added an example to the answer. – Martin Rosenau Jul 9 '17 at 20:06
• +1 for clarification; however, I will need more time to digest your example and verify that it is a correct answer to my question. – user84204884834329 Jul 9 '17 at 22:46

Starting point of your investigation could be Quartus's Tools -> Netlist Viewers -> RTL Viewer, find your 400 MHz signal on the map, and trace where it goes.

The 50MHz clock should be constrained at the output of the clock divider. Design Compiler does not calculate a clock division itself. It propagates the main clock (400MHz) or stops propagation to the rest of the circuit, but never propagates a 50MHz clock unless the user defines the required constraints.

• Hmm, interesting (+1). Two follow up questions please: (1) Is this documented somewhere in DC manual? (2) Is there a way to define the 400MHz as a master clock and the output of the clock divider as a secondary clock? (3) Please show how to constrain the 50MHz clock. – user84204884834329 Jul 10 '17 at 23:23
• DC's documents are not public and only distributed to customers, but other tool vendors also support Synopsys Design Constraints (SDC). For example, Xilinx has a document, just search create_clock and create_generated_clock commands in it. – ahmedus Jul 10 '17 at 23:39