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This question is an exact duplicate of:

I want a synchronous D-flip flop with three input,reset,D and CLK,but i can't find it,only four or two inputs,and four inputs just D,CLK,Set and reset ,but find the asynchronous D-flip flop with three input on the Internet.

Can i do anything to let asynchronous D-flip flop become synchronous D-flip flop ? For example,change NAND by AND .

Someone told me : take the 4 input one and ignore the set, that is, hold it false and remove any following logic that no longer changes state as a result,but i don't know last sentence meaning and the method.

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marked as duplicate by Andy aka, laptop2d, Dmitry Grigoryev, winny, PeterJ Jul 13 '17 at 13:41

This question was marked as an exact duplicate of an existing question.

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Just take a CD4013, or whatever series you're working with, and pull the set pin low.

CD3013 datasheet table

From: TI Datasheet

Edit: Also from the datasheet:

A high level at the SET or RESET inputs sets or resets the outputs, regardless of the levels of the other inputs. When SET and RESET are inactive (low), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The resistor and capacitor at the RESET pin are optional. If they are not used, the RESET and SET pin must be connected directly to ground to be inactive.

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  • \$\begingroup\$ pull the set pin low means pull the set pin become 0? \$\endgroup\$ – Shine Sun Jul 10 '17 at 23:34
  • \$\begingroup\$ Yes that's right. Tie it directly to ground. I edited the answer to quote this from the datasheet. \$\endgroup\$ – Blair Fonville Jul 10 '17 at 23:40
  • \$\begingroup\$ No, no, no. The CD4013 has asynchronous resets. A high on the reset will cause an immediate reset, and will not wait for the clock. \$\endgroup\$ – WhatRoughBeast Jul 11 '17 at 0:13
  • \$\begingroup\$ Can you give me synchronous D-flip flop schemaric with three input to let me know your explaination? \$\endgroup\$ – Shine Sun Jul 11 '17 at 0:13
  • \$\begingroup\$ @WhatRoughBeast yes, that is correct! Thanks for pointing it out. I took his question to mean he only wanted synchronous data, and intended to ignore the set pin. \$\endgroup\$ – Blair Fonville Jul 11 '17 at 0:39
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What you are asking for is called a synchronous reset, and as far as I know no simple flip-flops will do it. If you are using a power supply in the range of 2 to 6 volts, and are willing to to use an entire 16-pin DIP package for one logic line, you can use part of a 74HC162 or 74HC163.

schematic

simulate this circuit – Schematic created using CircuitLab

Note that the circuit will reset if a positive-going edge arrives while the reset line is low. If the reset line is high when a clock edge occurs, DIN will be transferred to DOUT and held until the next clock.

If you have several lines which you want to save using the same clock, but only a single reset which affects all of them at the same time, you can use the unused inputs (PB, PC and PD) which I have tied together and grounded here.

I've shown the power supply as 5 volts, but if you look up the data sheet you'll see that it can handle a 2 volt to 6 volt range - whatever you're using for the rest of your logic. Speed will be affected. Again - read the data sheet.

I suggest you look up the data sheet for the 74HC163, and work your way through the explanation which it gives.

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  • \$\begingroup\$ but as i know, 74HC162 or 74HC163 are counters,not D flip flop \$\endgroup\$ – Shine Sun Jul 11 '17 at 0:38
  • \$\begingroup\$ Yes, but not if you use it as I have instructed. Read the data sheet. Assume that I know what I'm talking about. After you have read and understood the data sheet you will see what I mean. \$\endgroup\$ – WhatRoughBeast Jul 11 '17 at 0:48
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schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ But there are four inputs now ,how should i delete S to let this DFF become synchronous D-flip flop with three input? \$\endgroup\$ – Shine Sun Jul 11 '17 at 1:04
  • \$\begingroup\$ "A FF is a sync data register, while SR are always async latches." not really true, although it can be in some cases. there are both synchronous and asynchronous set and reset signals; it just depends on the internal circuitry of the gate. there are also gated SR latches which are synchronous (and SR master slave flip flops). you have a pretty poor understanding of digital logic sequentials yet you always post the wrong things ... \$\endgroup\$ – jbord39 Jul 11 '17 at 1:04
  • \$\begingroup\$ @TonyStewart.EEsince'75: well you have known wrong for 40 years. i work as library designer and we release all sorts of latches and flops, today! you can read synopsys guides or modelsim, they all describe this and are industry standard. you are ignorant and made it, not correct. not sure why you are also so stubborn when clearly wrong. had to correct you in about 10 posts over the last year or so. if you ever read a single source i linked you would not be ignorant anymore. i really am confused why you are so stubborn on this point ... \$\endgroup\$ – jbord39 Jul 11 '17 at 1:31
  • \$\begingroup\$ @TonyStewart.EEsince'75: here you go, barrywatson.se/dd/dd_sr_flip_flop_master_slave.html master slave SR flip flop. wow it took an entire GOOGLE search top result to find an implementable schematic. synchronous set-reset flip flop: allthingsvlsi.wordpress.com/2013/04/06/… asynchronous set-reset flip flop: design-reuse.com/articles/37799/… \$\endgroup\$ – jbord39 Jul 11 '17 at 1:36
  • \$\begingroup\$ @TonyStewart.EEsince'75: I think you confuse the circuits you built out of discrete logic gates released by vendors with what you can do when you are printing on silicon. there are all sorts of gates. get woke son. \$\endgroup\$ – jbord39 Jul 11 '17 at 1:37

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