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I'm playing with some latching circuits :

  • circuit 1 - more details here

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  • circuit 2 - more details here

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Latching with these circuits works, but above a given input voltage ( > 30V for circuit 1, > 16V for circuit 2), I can latch ON but I cannot latch OFF.

For circuit 1, I've used : BC547B bipolar transistor, and FQP27P06 Mosfet P

For circuit 2, I've used : FQP27P06 Mosfet P and FQP30N06L Mosfet N

For both circuit, load is a DC-DC converter connected to a 5V microcontroller (drawing ~20mA), all components are put on a breadboard. Voltage is provided by a labo power supply. 10K resistors have been replaced by 15K.

Above a given voltage, both circuits cannot latch off. Here is a scope capture when I try to power off circuit 2 :

  • blue plot : load voltage
  • yellow plot : P mosfet gate
  • green plot : N mosfet gate

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here is a zoom for circuit 2 :

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we can see P channel gate voltage slowly decreasing. When N channel closes, it decreased to Max Value - 1.15V

When voltage is reduced to 7V latching works :

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How can we explain this behavior? How can I prevent it?

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  • \$\begingroup\$ Well there are alot of things that can go wrong with this circuit. I would start with the divider going to gate of the PMOS 15k & 100k still gives the PMOS a Vgs of 2.35V with an 18V supply. Add a few 15k in parallel so Vgs guaranteed lower than threshold voltage. \$\endgroup\$ – sstobbe Jul 11 '17 at 14:53
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Circuit 1: VGS max is rated as 25 volts for Q2. At 30 volts, your gate source junction is breaking down. Circuit 2: When you push the button to latch off, P channel voltage is momentarily pulled up to [power input - power input * 15K/(100K+15K)] as @sstobe says. At 16 volts, this is about 2 volts, so you never turn the MOSFET off (VGS(Th) can be 2 volts from data sheet). You have to pull the gate voltage up to within less than this value.

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  • \$\begingroup\$ Sure, both mosfets Vgs are above max rating. For my use case, I thought I could use it at 30V because I have a small load, but as you said, I can damage gate source junction. So far it still works! For circuit 2, as @sstobe and you said, when switch is closed, is pulled up to the value of 10k/100k voltage divider. In simulation, I modified R1 to 1k and R2 to 150k. Latch works up to 40V. In order to reduce Vgs voltage I found this option : mosaic-industries.com/embedded-systems/microcontroller-projects/… \$\endgroup\$ – rem Jul 12 '17 at 11:04

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