# verilog assign different width input

I have a module in verilog called jtag_sw that expects a 4 bit input. It is a mux. A smaller verison of the code is below as an example.

Only 3 signals [0:3] of JTAG_TDIare physicaly assigned to pins (by me). However, when I compile JTAG_TDI[4] is assigned to a random pin by Quartus, which I want to prevent. How could I do this? I think it is related to assigning different widths but I'm really not sure.

module test ( JTAG_TDI, DEB8_TDI);

output [3:0] JTAG_TDI;
input DEB8_TDI;

jtag_sw u7 (

.TDI_in(DEB8_TDI),
.TDI_out(JTAG_TDI), // 4 bit input

);


If you want to leave the pin in the top level of the design, but want Quartus to not route it to a physical pin, you can make a "Virtual Pin" assignment in the assignments editor.

Simply open the assignment editor in Quartus, then add a new assignment at the bottom by clicking in the empty row. Select "Virtual Pin" as the type, and the name of the pin in your top level design as the target (e.g. JTAG_TDI[3]). Set the value of the assignment to "On".

Alternatively, simply remove the pin from your design. For example:

output [2:0] JTAG_TDI;

...

input [2:0] JTAG_TDI;