I have a module in verilog called jtag_sw that expects a 4 bit input. It is a mux. A smaller verison of the code is below as an example.

Only 3 signals [0:3] of JTAG_TDIare physicaly assigned to pins (by me). However, when I compile JTAG_TDI[4] is assigned to a random pin by Quartus, which I want to prevent. How could I do this? I think it is related to assigning different widths but I'm really not sure.

module test ( JTAG_TDI, DEB8_TDI);

output [3:0] JTAG_TDI;
input DEB8_TDI;

jtag_sw u7 ( 

        .TDI_out(JTAG_TDI), // 4 bit input 


a) You need a pin assignment file, which is separate from your Verilog. Use Pin planner tasks window, early pin assignment to edit it graphically.

b) The JTAG pins are reserved, you can't use them in your code.


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