I have a module in verilog called
jtag_sw that expects a 4 bit input. It is a mux. A smaller verison of the code is below as an example.
Only 3 signals [0:3] of
JTAG_TDIare physicaly assigned to pins (by me). However, when I compile JTAG_TDI is assigned to a random pin by Quartus, which I want to prevent. How could I do this? I think it is related to assigning different widths but I'm really not sure.
module test ( JTAG_TDI, DEB8_TDI); output [3:0] JTAG_TDI; input DEB8_TDI; jtag_sw u7 ( .TDI_in(DEB8_TDI), .TDI_out(JTAG_TDI), // 4 bit input );