My question is about CPLDs in general, but take for example this cheap Xilinx one.

I understand that unlike a microcontroller, a CPLD does not have a clock; external edges activate the logic immediately, without waiting around for an interrupt dispatcher to create a context switch and call a function.

On the unit linked above, the "max" Tpd is shown as being 10ns. Does that mean it's literally anywhere from 0ns to 10ns on a given edge, or is it more consistent within a certain set of environmental conditions? Which conditions would affect that delay most heavily?


3 Answers 3


The delay specification in a CPLD is the maximum (i.e. worst case) pin-to-pin delay. That is, the maximum delay it takes for a signal "edge" to propagate from any pin to any other pin through the internal (combinational) logic.

Saying that a CPLD doesn't have a clock is misguided; you can use a pin as a clock input to feed sequential logic. Comparing it to a microcontroller is also not really suitable, since CPLDs implement hardware, not software.

  • \$\begingroup\$ I know that I can use one to implement something which depends on a clock (like I2C). The real meat of my question is, how dependable is that delay? I can build my circuit around an expectation that it will be 10ns, but are there factors would cause it to suddenly be 8ns or 5ns instead? \$\endgroup\$
    – mikepurvis
    Commented May 11, 2012 at 14:37
  • \$\begingroup\$ One of the reasons to use a CPLD instead of an FPGA (apart from cost) is that the delay is more predicatable. The delay specification is the worst case delay, it will not get worse than that under normal operation conditions. The delay can be better than 10ns, though. It's just the worst-case. \$\endgroup\$ Commented May 11, 2012 at 16:25
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    \$\begingroup\$ Right, but what circumstances would cause it to be better? "10ns or better" is not good enough when one is trying to exercise precise control. I'm trying to understand what factors would need to be controlled or calibrated for. \$\endgroup\$
    – mikepurvis
    Commented May 11, 2012 at 17:07
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    \$\begingroup\$ The delay could be anywhere between 0 and 10 ns. It will depend on things like doping of the crystal when the circuit in the chip is built, alignment accuracy between the layers when the chip is built, the route that the synthesizer choose from input pin to output pin, and temperature. The pin to pin delay is not meant to provide a time reference smaller than the max delay. \$\endgroup\$
    – user9224
    Commented May 11, 2012 at 17:28
  • \$\begingroup\$ @scorpdaddy That's great, though! All of those things are fixed at runtime except temperature, which has a maximum speed it is likely to vary at. If what you are saying is true, it's actually extremely deterministic. If such a system could periodically reverify its own calibration (say, at 1Hz), that would be more than enough to keep it accurate. \$\endgroup\$
    – mikepurvis
    Commented May 11, 2012 at 17:51

The statement "Unlike a microcontroller, a CPLD does not have a clock" is simply untrue. Speakig rather generally, they both have synchronous sytems as well as combinatorial ones.

Making a comparison about interrupts is also misleading. CPLDs don't normall run machine code, though machine code could be implemented in one (I used to teach a class on doing just that) So a CPLD could 'cause a context switch' if it were made to run machine code.

Tpd is Time-propogation delay (worst case). In PLDs is it a measurement to be taken with a big pinch of salt. This is because it's definition is completely down to the manufacturer.
It usually means the longest possible time, given worst case environmental conditions and manufacturing tolerances for a signal to travel from one pin via the shortest possible route to another.

In reality this usually means - pin->input pad->routing pool->output pad->pin.
Depending on the CPLDs architecture, routing pool may or may not include the LUTs (lookup tables) that form the internal logic facilities, and if it did it is most certainly the fastest route through it.

So really, Tpd is made up of a completely useless function for the PLD, a piece of wire with no logical functionalty!

If you want to get a better view of the speed of a PLD you need to examine it's manual for the 'Timing Model' this takes better account of the internal architecture to implement, e.g. a LUT-flip flop-routing pool that typically makes up the internals of any function.

To answer your last question, there are two variables that effect speed, Voltage and temperature. Lower voltage devices are generally faster. Internal resistances and thus the current available to charge a gate are affected by temperature. Higher temperature = more resistance = slower device.


It's a great question at first it is a big unknown until the design is simulated.

Added: THis simple answer is NO. THat only applies to prop delays from pin to pin for accessing the closest register. There is considerable more latency if you read all the specs on timing.

The designer must be aware of metastable conditions and race conditions in defining input and output states so the macrocell process works as required. It is also prudent to test the device using +/-% clock and +/-% V for fault margin.. i.e. test to failure or 15% max and verify that states are clocked in a timely fashion to prevent assumptions in timing errors.

Doesn't Xilinx tools have good simulation data to analyze this? But you are correct to beware that there will be latency, setup and hold time for each macrocell. It is also worth noting that the tradeoff between MC-LP and MC-HS is power and latency.

Clocking serial data is essential and knowing the jitter margin between data transitions and clock active edge. This is what turns digital communication into the analog world.

2nd Add: With respect to the latter question "Which conditions would affect that delay most heavily?"

As I indicated that there are two types of macro cells (MC) the ones obviously most critical for delay are the Low Power ones (LP)

MC's which contain large trees of boolean conditionals, or deeper trees, will create longer latency. Ripple counters are notorious for this latency.

Setup time is cell specific and similar to individual chips. A revue of these datasheets will give you more details.

Generally if process is complex in boolean logic & ripple counters delays, then it is necessary to synchronize the state into Latches. THis adds controlled latency but prevents race conditions and is the basics of a State machine. Events can be processed depending on combinational inputs, outputs or intermediary states. Clocking these states into latches, aka FF's or hardware "registers" for further processing with more logic before the next clock cycle. Look up Finite State Machine theory and design methods to gain insight here.**

  • \$\begingroup\$ Although the issues you discuss here I find interesting I am not sure how they relate to the question that was asked, am I just not deep enough in the field to understand? \$\endgroup\$
    – Kortuk
    Commented May 12, 2012 at 2:02
  • \$\begingroup\$ Dear Kortuk, His assumptions were wrong and yours were correct. Having designed a head mounted video display that takes analog inputs and synchronizes the the CPLD created all the logic statements I design to multiplex the analog signal to rows and columns of pixels on an AM-LCD VGA display in a 1cm chip magnified by a lens. If you dont understand the field, just ask. My answer was deeper than your understanding. try again. \$\endgroup\$ Commented May 12, 2012 at 2:59
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    \$\begingroup\$ I actually understood what you said, and your comment verifies that, I was seeing a very simple question from the poster and a somewhat convoluted answer from you. It seems you have now added a clear statement answering the question. On that note, you may have a decent bit of experience but experience does not help others without communication allowing them to learn from it. \$\endgroup\$
    – Kortuk
    Commented May 12, 2012 at 3:10

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