It's a great question at first it is a big unknown until the design is simulated.
Added: THis simple answer is NO. THat only applies to prop delays from pin to pin for accessing the closest register. There is considerable more latency if you read all the specs on timing.
The designer must be aware of metastable conditions and race conditions in defining input and output states so the macrocell process works as required. It is also prudent to test the device using +/-% clock and +/-% V for fault margin.. i.e. test to failure or 15% max and verify that states are clocked in a timely fashion to prevent assumptions in timing errors.
Doesn't Xilinx tools have good simulation data to analyze this? But you are correct to beware that there will be latency, setup and hold time for each macrocell. It is also worth noting that the tradeoff between MC-LP and MC-HS is power and latency.
Clocking serial data is essential and knowing the jitter margin between data transitions and clock active edge. This is what turns digital communication into the analog world.
2nd Add: With respect to the latter question
"Which conditions would affect that delay most heavily?"
As I indicated that there are two types of macro cells (MC) the ones obviously most critical for delay are the Low Power ones (LP)
MC's which contain large trees of boolean conditionals, or deeper trees, will create longer latency. Ripple counters are notorious for this latency.
Setup time is cell specific and similar to individual chips. A revue of these datasheets will give you more details.
Generally if process is complex in boolean logic & ripple counters delays, then it is necessary to synchronize the state into Latches. THis adds controlled latency but prevents race conditions and is the basics of a State machine. Events can be processed depending on combinational inputs, outputs or intermediary states. Clocking these states into latches, aka FF's or hardware "registers" for further processing with more logic before the next clock cycle. Look up Finite State Machine theory and design methods to gain insight here.**