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schematic

simulate this circuit – Schematic created using CircuitLab

Suppose we have simple same here. The logic behind this is very simple. During MCU boot it tests pins CONF1 and CONF2 for data on it (LOW or HIGH) and configures its internals based on this. Also during the startup sequence it holds BOOT_COMPLATE HIGH for example. After MCU goes into ready state it drives BOOT_COMPLATE in the opposite direction (LOW in this example). After that pin on the MCU are used for DATA1 and DATA2 functionality. Vendor of MCU advises to use CPLD for this kind of work. But provide no shame for free. My thoughts about how this should work and looks like all together:

schematic

simulate this circuit

  1. Power up CPLD first (assume we have the proper program already set up in it)
  2. Drive IO2 and IO3 LOW or HIGH as needed by config
  3. Test signal level on IO1 and wait for LOW in this example (indicates MCU boot complete)
  4. Set IO2 and IO3 tri-stated (floating)
  5. Done? Or am I missing something?

Also it would be nice to have VHDL or SystemVerilog example for this simple situation

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It looks fine to me. It fits with the description you gave. I think this is basically what the MCU vendor had in mind.

Only additional thing you should consider, is what are the "Other components" do during the boot period. More specifically, how do they influence the CONF1/CONF2 signals. It could be that they also pull the lines to one direction (not actively of course, but due to internal pull-up/down or through the ESD diodes).

If it is the direction that suits you (the same as the CPLD) then all is ok. If not, there could be problems, depending on which side pulls stronger. If this is the case, you could/should use "isolating" components between the "Other components" and your MCU/CPLD structure.

That is most commonly series resistors that limit the current and thus the influence that the "Other components" can have to the configuration signals during boot.

OFF-TOPIC: I'm just asking myself why do they recommend to use a CPLD for something that simple?! Why can't you just use fixed pull-up or pull-down resistors?

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  • \$\begingroup\$ It is simple here to make example clear. In general, there is not MCU but a processor with more than 20 Config pins which have other signals multiplexed. Also nice point about other components. \$\endgroup\$ – Alexey Smirnov Jul 12 '17 at 14:53
  • \$\begingroup\$ @AlexeySmirnov You mean regarding the off-topic comment? But still, it doesn't make sense to me. I am using all the time processors that have around 30 config pins and I always use pull-up/down resistors. Never saw a recommendation for a CPLD. I guess it is more flexible if you need to change sth. In my case I have to change the resistors that are placed. \$\endgroup\$ – nickagian Jul 12 '17 at 15:00
  • \$\begingroup\$ Hm... Maybe I don't understand something. Indeed, I don't need the flexibility of reconfiguring CONFIGS. So resistor would be fine. But I think that if I connect pull-up for example to pin CONFIG1 and connect it to VCC it will stay HIGH forever even if DATA1 sends LOW while normal operation. So I need CPLD to overcome this. Am I wrong? \$\endgroup\$ – Alexey Smirnov Jul 12 '17 at 15:09
  • \$\begingroup\$ @AlexeySmirnov Don't get me wrong, I didn't say you don't understand sth :-). It is more about the vendor's recommendation. But it could be a special requirement for the signals that are normally present there. Nevertheless, you are wrong about the other point. The pull-up will certainly not prevent the signal to go LOW during normal operation. If either side pulls LOW, the line will indeed go LOW! Nothing will stop it from doing it. You'll just have a higher power consumption due to the current flowing from VCC to GND over the resistor. \$\endgroup\$ – nickagian Jul 12 '17 at 15:22
  • \$\begingroup\$ Got your point. What about clock signals? For example, we have CONFIG and CLOCK multiplexed. If we pull config HIGH will it affect CLOCK operation after MCU switch from CONFIG to CLOCK pin state? Will the CLOCK signal be distorted in some way? \$\endgroup\$ – Alexey Smirnov Jul 12 '17 at 15:43

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