Suppose we have simple same here. The logic behind this is very simple. During MCU boot it tests pins CONF1 and CONF2 for data on it (LOW or HIGH) and configures its internals based on this. Also during the startup sequence it holds BOOT_COMPLATE HIGH for example. After MCU goes into ready state it drives BOOT_COMPLATE in the opposite direction (LOW in this example). After that pin on the MCU are used for DATA1 and DATA2 functionality. Vendor of MCU advises to use CPLD for this kind of work. But provide no shame for free. My thoughts about how this should work and looks like all together:
- Power up CPLD first (assume we have the proper program already set up in it)
- Drive IO2 and IO3 LOW or HIGH as needed by config
- Test signal level on IO1 and wait for LOW in this example (indicates MCU boot complete)
- Set IO2 and IO3 tri-stated (floating)
- Done? Or am I missing something?
Also it would be nice to have VHDL or SystemVerilog example for this simple situation