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I am working on implementing a disciplined oscillator to increase the accuracy and long-term stability. The oscillator would be a VCTXO running at about 25 MHz. My thought is to have a 32-bit counter that would count each clock cycle. A GPS 1PPS would be used as the time reference and counting would begin on a given pulse. After a number of pules (maybe one, maybe 100, maybe some other value), the count would be read out by a micro controller and a feedback signal generated to either slow or speed the frequency of the VCTXO.

As a more concrete example, a 25 MHz oscillator would ideally have exactly 2,500,000,000 pulses in a 100-second period. But the actual count will certainly be either high or low. Based on the actual count, a correction signal would be applied to the VCTXO to speed it up or slow it down. The long term oscillator stability and accuracy would thus be linked to the time reference

My main difficulty is finding a suitable counter.

  • I would like something that is 32-bit (gives something like 200 seconds between rollover).
  • The counter should be small. I'm developing for a low-power mobile device. A single ic 4 to 7 mm in size would be ideal.
  • Ideally, counter readout would be over SPI to support the current micro controller. For size and simplicity, I would prefer not to use a parallel bus to read out the counter value.
  • Thoughts on synchronous vs asynchronous counters?

I am open to different technologies that could be used as the counter (separate micro, FPGS, CPLD, Flip-flop array, etc.) Please give suggestions on how to implement.

I did come across the LS7366R-TS (http://www.lsicsi.com/pdfs/Data_Sheets/LS7366R.pdf) which seems like something that might work, but I cannot seem to find it for sale anywhere. I've contacted the company and not yet heard back. But I also wonder if there are alternatives ic's and methods that might be better suited and more readily stocked. Please let me know if I need to further clarify the problem.

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    \$\begingroup\$ Consider using a pre-scaler to divide down the oscillator frequency to something like 97.65625 kHz (25 MHz / 256), and then use a micro to count the output of the prescaler. \$\endgroup\$ – The Photon Jul 12 '17 at 18:02
  • \$\begingroup\$ @The Photon : Yes, reasonable solution, but that would also increase the fractional uncertainty by the pre-scale factor (i.e. 256 pre-scaler would mean 256 times more uncertainty in the measurement). \$\endgroup\$ – py_man Jul 12 '17 at 20:02
  • \$\begingroup\$ usually you need to average your correction signal over many cycles of the reference clock to avoid over-correcting anyway. If you are at ~100 kHz and comparing with the GPS 1 pps clock, then over 10 s you are looking at ~1 ppm error due to pre-scaling. \$\endgroup\$ – The Photon Jul 12 '17 at 20:15
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    \$\begingroup\$ @py_man - your concern about loss of resolution is true as far as it goes, but meaningless without more detailed system specification. If the VCTXO has +/-100 ppm compliance, and you use a 10-bit DAC as input, the control resolution is about 5 Hz, (25,000,000 x 200 x 10^-6 / 2^10) so factor of 4 prescaler won't hurt. You need to look closely at your system components and figure what your constraints are. \$\endgroup\$ – WhatRoughBeast Jul 12 '17 at 21:19
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    \$\begingroup\$ The correct way to design an ultrastable Osc ( or anything for that matter) is to give specs or requirements. Osc specs are given in ppm for tolerance/stability/aging and temp range then phase noise. You have given none of these. I have designed dozens of XO's from PLL OCXO's, TCVCXO, VCXO TCXO and fractional N Synth's with sync on VLF, WWVB , GPS 10MHz or 1pps and NIST time-web-sync . So pls define your list of specs. and limitations to access for a sync ref. \$\endgroup\$ – Sunnyskyguy EE75 Jul 13 '17 at 3:48
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It's extremely difficult to find a microcontroller on the market these days that does not have some kind of counter/timer module built into the chip — usually they have several, because they are so universally useful. And unless you pick a very small, low-power µC, it will have no problem counting at 25 MHz.

If the hardware counter does not have enough bits, use it as a prescaler and do the rest of the counting in software. Use the counter overflow interrupt to increment a software counter, and combine the results as needed.

So, just connect your oscillator to the counter clock input, and configure the counter to free-run. Connect the GPS 1 PPS signal to an interrupt line. Each time the interrupt fires, read the counter. Subtract the previous reading from the current reading to find out how many oscillator cycles have elapsed in the current GPS second (accounting for roll-over, of course). Use this value to compute the next control voltage update.

And you will want to do this every second. Trying to average the count over hundreds of seconds may seem like a good way to get higher precision, but in fact, it will make the system very slow to correct itself after external perturbations (e.g., temperature and voltage changes).

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  • \$\begingroup\$ Thanks for the comment Dave. I am using one of the MSP430 microcontrollers and unfortunately it has a 16 MHz maximum MCLK. And I imagine this would not be able to count the 25 MHz clock. It's possible to switch uC's but that would not be ideal because of the overhead involved with re-doing the firmware. \$\endgroup\$ – py_man Jul 12 '17 at 19:58
  • \$\begingroup\$ @py_man - Then use half of a dual flip-flop to divide the 25 MHz to 12.5 MHz. This is what Dave meant by "prescaler". \$\endgroup\$ – WhatRoughBeast Jul 12 '17 at 20:53
  • \$\begingroup\$ @WhatRoughBeast - Is it true that 16MHz MSP430 would be able to count every 12.5MHz clock cycle? I think that's right, just wanted to make sure that there wouldn't be any dropped clock cycles using the on-chip timers. If no dropped counts, this would be a very easy way to go. \$\endgroup\$ – py_man Jul 12 '17 at 22:02
  • \$\begingroup\$ @py_man - I have no idea. I've never used the family. I was just pointing out that the 16/25 issue is easily overcome. The rest is up to you. \$\endgroup\$ – WhatRoughBeast Jul 12 '17 at 22:56
  • \$\begingroup\$ Does it have to be 25 MHz? Why not just discipline the CPU's own oscillator? \$\endgroup\$ – Dave Tweed Jul 13 '17 at 2:44
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I did sonething like that a while ago. It is a Tyco high stability vctcxo disciplined by a GPS. One of The mcus is configured as a phase comparator and another as counter frequency generator.

I can post a link later.

Edit: couldn't find the link any more but here is the gist of the project.

The goal was to produce any arbitrary frequency generator from a fixed oscillator being disciplined by a GPS 1pps signal.

It consists of two mcus.

Mcu1 uses the main oscillator as its clock (a tco919r high stability vctcxo. It is a sonet oscillator). This mcu does two things. 1. It divides us the oscillator frequency via a own generator and 2. It produces a 1pps signal, to be compared to the GPS 1pps signal

Mcu2 compares the two 1pps pulse train. It is essentially a counter whereby the counting is started by one pulse train and ends by the other. The count is then used as a duty cycle to drive a own generator whose output goes through a lpf onto the vctrl pin of the vctcxo.

Minimalist implementation, very simple to implement. The whole thing takes 10 to 15 seconds to lock. Probably the simplest gpsdo you can find.

The two mcu set up was necessary to reduce jitter.

Hope it helps.

Edit 2: I lied about being unable to find the li k. Here it is https://www.eevblog.com/forum/projects/toyo-tco-919-%27high-stability%27-crystal-oscillators/15/

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  • \$\begingroup\$ A plug for the tco919. It is one amazing tcxo. I have thrown it in all places, in a freezer, under a hair dryer, I. Direct sunlight, .... \$\endgroup\$ – dannyf Jul 12 '17 at 21:32
  • \$\begingroup\$ Still, its output remained rock solid. I guess it is the benefit you get for a sober oscillator. \$\endgroup\$ – dannyf Jul 12 '17 at 21:32

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