# Capacitive Voltage Divider and Discrepency in Output Signal

Background
I designed a capacitor voltage divider for the purpose of measuring the voltage step up of a resonator. Before I measure the voltage step up I wanted to measure the voltage divider ratio to ensure it matches the theory.

My Circuit and Theory Result
(LTSpice Parameters: Vin = Sinewave,5Vpp,@ 40MHz)

Theory $$V_{out}=\bigg(\frac{C_1}{C_1+C_3}\bigg)\cdot V_{in}= \frac{V_{in}}{V_{out}} =~ 76$$

Physical Measurement

• Signal generator parameters (Sinewave, 5Vpp, 40MHz)
• Measured output with Oscilloscope (Input Impedance = $$\10M\Omega, 13pF\$$)
• Result: $$\V_{in}=5V, V_{out}=0.2V\$$. Hence $$\\frac{V_{in}}{V_{out}}= 25\qquad\$$ [$$\32\%\$$ off!]

Question: Why is my measurement of the output voltage of my capacitor voltage divider not matching the theory? Is there some parasitic capacitance or some problem with my measurement technique that I am not taking into account? Thanks for the help.

• Think about "parasitic resistance". When you measure something you need to take some electrons. And whatever you measure with probably steal some, there's never any infinite impedance on an OP-amps inputs. Jul 14, 2017 at 4:26
• Add 13 pF and 10 M in parallel with C3, since that is what the scope presents. Also, your theory should read C3/(C1 + C3). Jul 14, 2017 at 4:28
• But the input impedance of the o.scope (10MOhm) is so much greater than the capacitor configuration(16KOhm, @40MHz) it shouldn't matter. Also, no the equation for impedance is Vout = Z3/(Z1+Z3) NOT the equation for capacitance: Vout = C1/(C1+C3). Jul 14, 2017 at 5:03
• just an aside that ltspice uses the prefix m or M for milli, for x10^6 the prefix is Meg Jul 14, 2017 at 5:04
• with parasitic capacitances in the many pFs, it's very difficult to make accurate measurements on the bench with compponents that small Jul 14, 2017 at 7:37

A problem is that LTSpice doesn't like "MHz" for what you think. Instead, LTSpice thinks you meant milliHertz, when you wrote it out that way.

Regarding syntax here, you can use Mathjax (I think it's called that.) Or, at least, the version of it they support here. You use either "\$" to bracket an in-line equation, or "" to bracket a block equation. See this link: MathJax basic tutorial and quick reference for some good info to try out. Regarding your scope measurement, I don't know. I think you are saying that you are measuring way more than you expect. Is that correct? Is this on a solderless breadboard? If so, there is capacitance there (significant enough in your case, as I've seen figures in the several pF range) and it may be affecting$Z_1$far more than$Z_3$. • No, unfortunately that had no effect. Also, I built and measured this actual voltage divider circuit with a signal generator and o.scope and found the same results. Jul 14, 2017 at 5:10 • @JGiles You need to do the same for your .AC statement, in case that's it. As far as LTSpice's results, I get about$46.6\:\textrm{mV}_\textrm{RMS}$at the divider point with LTSpice, relative to ground, and I compute about$46.7\:\textrm{mV}_\textrm{RMS}$. Close enough. – jonk Jul 14, 2017 at 5:20 • @JGiles Or peak, I compute$66\:\textrm{mV}_{PK}\\$. Which is what LTSpice's .AC mode tells me if I plot it as linear.
– jonk
Jul 14, 2017 at 5:27
• Right. That is also what I got with my LTSpice model, and mathematical model. But the measurement does not agree with the model. Which suggests I am missing some stray capacitance, inductance, or am doing some thing wrong with my measurement technique. Jul 14, 2017 at 7:02
• As @jonk already told you, if you are measuring this on a solderless breadboard, this could introduce way too much parasitic capacitance. Try to build your circuit on a piece of FR4 material using the so-called "dead bug" technique. Jul 14, 2017 at 8:13

Measured output with Oscilloscope (input Impedance = 10MOhms, 13pF)

Assuming you chose a frequency that is high enough to avoid the loading effects of the 10 Mohm resistor you hit the next problem and that is the input capacitance of your scope probe.

13 pF in parallel with 18.7 pF is going to wreck your measurements but in the wrong direction so I have to assume that the 0.25 pF capacitor feeding the 18 pF is badly affected by parasitic capacitance in your set-up.

0.25 pF is round about the self capacitance of an 0805 surface mount component and it's really easy to add another 0.5 pF just by not paying attention to how you build things.

• Well, at 40MHz the (Z3+Z1) ~ 16KOhms. Relative to the 10 Mohm from the probe would the circuit be loaded? Also, how would you model the self capacitances and parasitic capacitances (series, parallel, combination with C1,C3)? Thanks! Jul 15, 2017 at 4:34