I'm trying to understand how an I2C master module (in Verilog) works.

I've found in Github this module, which seems not too much complex. https://github.com/manojvishy/I2C_Project/blob/master/i2c_master.v

It has an input called open_drain which always is at high level in its testbench.

I can't figure out for what does it worth.

Any idea?

  • \$\begingroup\$ VTC - Unclear what you are asking. Get the free spec for I2C, which can be found in a plethora of places on the web, and read up on how all aspects of the interface protocol work and then work out what that design does. You should be able to do this on your own without a lot of help. \$\endgroup\$ Commented Jul 14, 2017 at 12:49
  • \$\begingroup\$ It appears to select whether the SCL pin should be a open drain pin or push pull. \$\endgroup\$ Commented Jul 14, 2017 at 14:15

1 Answer 1


The code in the module gives you a pretty good idea as to what this does, it selects between whether the output is being pulled high or if its sending data.

With the open_drain signal you can pull the outputs high external to the module.

input open_drain, // Open drain

assign scl_out = open_drain ? 1'b0 : scl_count[1];

Another note is on some FPGA's you will need an additional module that changes the pin into a high impedance state required by I2C.


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