# Sensitivity list rule in HDL

I have a little confusion about sensitivity list rule: all signals that are read in the always block must be included in the list. When including the posedge CLK and EN in my sensitivity list, I get value of x changed when either of signals in the sensitivity list changes. Thus, if EN changes in the middle of the clock cycle, x changes accordingly, which is expected. However, this is not the outcome I wish to get:

always @(posedge CLK, EN)
if(EN)
x <= 1;
else
x <= 0;


I need the value of x to change only at the rising edge. Therefore, I remove the EN from the list to achieve desired outcome. But then, this violates the rule.

This is, probably, a very trivial question, but could someone clarify what's the proper way to implement it?

Forget that rule. Here's a simpler one:

• If you want sequential logic, use always @(posedge clock) (or negedge). You don't need to mention any other signals in the sensitivity block.

(You can sometimes also use sensitivity lists like always @(posedge clock or posedge reset) for reset signals, but don't try to get too fancy. It's very easy to create something that won't synthesize.)

• If you want combinational logic, use always @(*).

This is a shorthand (introduced by Verilog-2001) that makes the block sensitive to every signal that's used in it. There's no reason to name every signal anymore -- that syntax is obsolete and unnecessary.

That rule is just for combinational logic, when the outputs are solely dependent on the current state of the inputs. Verilog 2001 added the @(*) syntax that automatically figures out the sensitivity list for you, and SystemVerilog added always_comb to capture your intent for the block (and also handle blocks that turn out to have constant inputs)

For synchronous and asynchronous blocks, you add just those signals involved with the synchronization to the sensitivity list. All of the other inputs will be synchronized to those signals. In your case, EN should only be sampled on the posedge CLK.

You can use always_ff@(posedge clk) to infer a sequential logic without having to worry about the EN sensitivity. Or using always@(posedge clk) can also be good.

Only for combinational logic, is the EN also needed to be included in the sensitivity list using always_comb