# Voltage Multiplier Circuit Problem

I have gone through Volatge multiplier circuits like, doubler ,tripler, quadrupler. And seem to understrand circuits like them shown in the figure.

With these in mind, I find it very difficult to apporach these circuits shown below. What are thing I have to keep in mind solving them? And I dont know how approach these power sources.

• The shared centre Cap becomes the best DC stored cap chain, while the outer ones carry AC + DC clamp and step, repeatedly . Try my simulation. tinyurl.com/ycscgmqb You can move the wire around or add scope probes or as many bridges as you can centre on the page. – Tony Stewart Sunnyskyguy EE75 Jul 15 '17 at 21:19
• @TonyStewart.EEsince'75 I read few more articles and what i seem to get from them is, adding the lower part just doubles the frequency. And this reduces ripple. This doesn't increase the output voltage. But, can you just elaborate which cycle charges which capacitors up? I mean, for the half wave circuits, I can easily say step by step, this capacitor charges in positive, this in negative, like that. But I cannot explain this full wave circuit. Do the both of first capacitors from the upper and lower half charges simultaneously? – Rayhan Rashed Jul 16 '17 at 9:08
• The full wave just works on each polarity sharing the centre cap for DC and clamping the forward voltage on the upper and lower caps as half wave for each polarity, so the centre cap stores Vp for each half wave thus n Caps give n* Vp(sine in) minus the load decay seriesC* R decay % on last stage. Each diode acts as a single CLamp voltage on the AC waveform relative to the previous stage DC voltage in the centre caps. So outer caps have AC pulse +DC and inner caps have DC with just the ripple of Vp-decay voltage, all relative to the 0V tap. – Tony Stewart Sunnyskyguy EE75 Jul 16 '17 at 16:05
• The limits on cascade n depend on leak/ESR ratio and load/(ESR+Zc(f)) ratio for a string of caps n*C, and the higher initial tap voltage increases output proportionally. Higher f requires lower C values so a chopper DC-DC results in smaller topology values for energy out. it one wanted say 1A out at 50kV, 50Hz is not the way to do it rather use 50kHz. – Tony Stewart Sunnyskyguy EE75 Jul 16 '17 at 16:09