I was wondering what influences the max clock speed and how to calculate it for a circuit implementation. Let's take a CPU for example:
From what I understand the clock speed has to be choosen so that an input signal can propagate through the CPU in a way that all gates (and especially those on the "critical path") have enough time to stabilize their outputs. Therefore the design (determining the "critical path") and the propagation delay seem to be important for determining max clockspeed. However this leaves a lot of open questions on my side:
- How can I determine the propagation delay of a single gate?
Is the propagation delay dependent on the manufacturing process? (I'd guess so... e.g. I would assume that 10nm manufacturing results in lower propagation delay than 100nm manufacturing)
Are there reference values for propagation delays with different manufacturing process? Is it really as simple as I outlined or am I missing relevant factors? (max speed = delay * gates within critical path)
- How big is the variance between propagation delay of gates within the same manufacturing process (in state of the art 10nm manufacturing for example)
- Could I determine the gates within the critical path of an let's say a current i7 cpu by dividing its clockspeed through the assumed propagation delay or will I come up with a significantly wrong result?