I was wondering what influences the max clock speed and how to calculate it for a circuit implementation. Let's take a CPU for example:

From what I understand the clock speed has to be choosen so that an input signal can propagate through the CPU in a way that all gates (and especially those on the "critical path") have enough time to stabilize their outputs. Therefore the design (determining the "critical path") and the propagation delay seem to be important for determining max clockspeed. However this leaves a lot of open questions on my side:

  1. How can I determine the propagation delay of a single gate?
  2. Is the propagation delay dependent on the manufacturing process? (I'd guess so... e.g. I would assume that 10nm manufacturing results in lower propagation delay than 100nm manufacturing)

  3. Are there reference values for propagation delays with different manufacturing process? Is it really as simple as I outlined or am I missing relevant factors? (max speed = delay * gates within critical path)

  4. How big is the variance between propagation delay of gates within the same manufacturing process (in state of the art 10nm manufacturing for example)
  5. Could I determine the gates within the critical path of an let's say a current i7 cpu by dividing its clockspeed through the assumed propagation delay or will I come up with a significantly wrong result?
  • \$\begingroup\$ Data sheets, data sheets, data sheets. \$\endgroup\$
    – Andy aka
    Jul 16, 2017 at 9:50

2 Answers 2


--- prop delay of gate? At what voltage, what Cload, what inputSlewRate? Is gate crafted for minimum shootthru charge, or min delay?

--- yes, the fab's secrets produce different timing results

--- reference results? sure. You can always tweak the W/L in older processes. In newest, the optics of the exposure machines may constrain your choices, what with diffraction-limited layout.

--- How simple? The fanin, the fanout, the length of metal, if poly (HighR) is used, the # bulk ties to constrain charge upsets (jitter).

--- How big a variance? In older processes, between 1volt and 6 volt VDD, the delays easily are 100:1. In some cases, you want ~~ zero rail upsets (for AutoZero opamp internal clock generation), and very slow gates/FFs are fine.

--- Can I determine the # gates------lotta other factors: bus fanout, for example.



  1. Delay of a "single gate" should be listed in manufacturers specification. However, there are gates with different drive strength, and connection wires will have different length and therefore different capacitance. So the delay can be determined only after the layout is done.

  2. Yes, in general the gate prop delay is a function of transistors. There are plenty of reports on this. For the same manufacturing node a foundry usually offers several different libraries for skewed process, "fast (but power hungry)", normal, slow (but low power), etc..

  3. Reference values for prop delays are just ballpark references. While a design house might impose internal discipline to limit the depth of combinatorial logic in their designs, the final result can only come from a deep CAD-based analysis of fully routed design.

  4. How big is the variance within the same modern process? Ever wonder why the Intel's "10nm" process is delayed for three years now?

  5. Can you accurately determine the # of gates in i7? Likely not, because the wire delays dominate. And why would you need this anyway?


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