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I have following design and need to insert pipeline stage between components A and B (design doesn't meet timing constraints in Quartus II due to long data path between them)..

design block diagram

Simple register won't do since interface (basically simplified AMBA AXI4-Stream with START of frame signalization) between them is handshaked (B sets READY signal when it completes work on data and is ready to receive another). Work usually happens in one clock tick (so READY is almost always high) but it doesn't have to be and I need general solution to use throughout my design.

What do you (or industry) use in these cases? I don't really want to reinvent the wheel :)

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  • \$\begingroup\$ so, I don't fully understand the problem you're facing – is it that your design doesn't meet timing, or something else? And: if it's timing, why is it related to the AXI bus? \$\endgroup\$ – Marcus Müller Jul 16 '17 at 16:48
  • \$\begingroup\$ @MarcusMüller Well the path (mostly interconnect in FPGA) is too long, so I'd like to add pipeline stage to cut it into two paths.. And I'd like to do it in top level (without semantics change), instead of rewriting problematic component (to have output/input as register would require fundamental change in FSM). If I simply put a register there, component A would get READY change with delay (so it would send two data words instead of one, for example). \$\endgroup\$ – David Novák Jul 16 '17 at 16:58
  • \$\begingroup\$ sooo... an AXI FIFO? But really, it's not usual that the AXI in and outputs are not buffered by registers, and changing that would definitely a worthy change to the components in question. Unless I misunderstand what "the path" is – I assume it's the combined logic of A's tdata drivers and B's tdata consumers. \$\endgroup\$ – Marcus Müller Jul 16 '17 at 16:59
  • \$\begingroup\$ @MarcusMüller Yes, that makes sense.. Whole design is actually FIFO <- logic <- logic <- FIFO. Destination FIFO sets READY signal and logic closer to it does it as well (it inserts one word before first word of frame so it has to drop READY signal). I didn't make them buffered in a hope that path will be short enough (every resource on FPGA is precious).. \$\endgroup\$ – David Novák Jul 16 '17 at 17:29
  • \$\begingroup\$ well, now the not-buffering falls on your feet, because your path gets too long; I guess you know what you need to do. \$\endgroup\$ – Marcus Müller Jul 16 '17 at 17:38
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AXI stream requires a skid buffer that can store two data words. Here is as example of an AXI stream skid buffer in Verilog: https://github.com/alexforencich/verilog-axis/blob/master/rtl/axis_register.v

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