Microchip is offering a number of serial SRAM chips with a communication protocol called SQI which is similar to SPI but with 4 parallel bits written at each CLK toggle.
If you can spend the extra 3 pins this makes sense. You can achieve a throughput of 4 times the rate of SPI.
However there is a catch - SPI is supported by all modern MCUs as a hardware module so it runs automatically and very quickly and CLK rates of several MHz are not a problem.
SQI is not supported by hardware so you have to bit bang the protocol. If my MCU, for example, runs on an 8MHz system clock and it is executing most instructions in a single cycle (AVR) I can expect SQI CLK rate of under 1MHz. This is based upon software SPI implementation which is also sub 1MHz and has slightly less code in it.
So let's say I can transfer 4 bits at a time, using SQI, with 800 KHz CLK (real world numbers), that is 3.2 Mbits per second. However I can run SPI at 5MHz and get 5Mbits of data with less code and without having to wait with my application code while data is being sent or received over the communication lines.
So what is the point here? What am I missing?