Ignoring the details of the specific transmission in question (which @alex.forencich has already discussed in considerable detail), it seems like it's probably useful to consider the more general case.
Although this particular transmission hit 255 Tbps through the fiber, extremely fast fiber links are already in regular use. I'm not sure exactly how many deployments there are (probably not very many) but there are commercial specifications for OC-1920/STM-640 and OC-3840/STM-1280, with transmission rates of 100- and 200-Gbps respectively. That's roughly three orders of magnitude slower than this test demonstrated, but it's still quite fast by most ordinary measures.
So, how is this done? Many of the same techniques are used. In particular, pretty much everything doing "fast" fiber transmission uses dense wave division multiplexing (DWDM). This means, in essence, that you start with a (fairly) large number of lasers, each transmitting a different wavelength of light. You modulate bits onto those, and then transmit them all together through the same fiber--but from an electrical viewpoint, you're feeding a number of completely separate bit streams into the modulators, then you're mixing the outputs optically, so all those different colors of light go through the same fiber at the same time.
On the receiving end, optical filters are used to separate the colors again, and then a phototransistor is used to read an individual bit stream.
Although I've shown only 7 inputs/outputs, real systems uses dozens of wavelengths.
As to what it takes on the transmitting and receiving ends: well, there's a reason back-bone routers are expensive. Even though a single memory only needs to feed a fraction of the overall bandwidth, you still typically need pretty fast RAM--quite a bit of the faster parts of routers use pretty high-end SRAM, so at that point the data is coming from gates, not capacitors.
It's probably worth noting that even at lower speeds (and regardless of physical implementation such as DWDM) it's traditional to isolate the highest speed parts of the circuit to a few, small parts. For example, XGMII specifies communication between 10 gigabit/second Ethernet MAC and PHY. Although the transmission over the physical medium is a bitstream (in each direction) carrying 10 gigabits per second, XGMII specifies a 32-bit wide bus between the MAC and the PHY, so the clock rate on that bus is approximately 10 GHz/32 = 312.5 MHz (well, technically the clock itself is half that--it uses DDR signaling, so there's data on both the rising and falling edges of the clock). Only inside the PHY does anybody have to deal with a multi-GHz clock rate. Of course, XGMII isn't the only MAC/PHY interface, but most are similar in this respect--i.e., all of them have a wider interface at a lower clock, then the PHY puts those N parallel bits together into a single stream of bits for transmission over the medium (e.g., Gigabit Ethernet defined GMII using an 8-bit wide bus at 125 MHz).