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If I want to process data in the order it arrives, it seems that a FIFO would be most appropriate; however, I want to look over the data multiple times (at least 20 times), so I am considering either rewriting to the FIFO when I read from it or using RAM, which I can read from many times.

The data are points and I want to compare them with another set of points to identify ones that are within a certain distance.

My question is what are the benefits of each in terms of complexity, time, usage of FPGA resources, etc? I plan on using a Xilinx FPGA (likely kintex 7) if that is relevant.

Thanks

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Usually a FIFO is built around a simple dual port RAM. So it either consumes exactly the same resources (if you use hard FIFO logic) or slightly more (if you use soft FIFO logic) compared with a RAM of the same capacity. If you need data more than once, maybe a bare RAM makes more sense than a FIFO. Or perhaps several FIFOs back-to-back. Or just a register pipeline. Really depends on exactly what it is you want to do.

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  • \$\begingroup\$ What do you mean by soft vs hard logic? \$\endgroup\$ – Ethan Jul 17 '17 at 20:03
  • \$\begingroup\$ Block RAMs on some FPGAs contain 'hard' FIFO logic and can be directly used as FIFOs without using any additional logic resources. Some FPGAs do not support this. Or maybe you need to do something that the hard logic does not permit, or you just like implementing it yourself. In which case, the FIFO pointer manipulation logic will take up some additional logic resources above and beyond the RAM. \$\endgroup\$ – alex.forencich Jul 17 '17 at 20:07

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