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I'm looking for a way to transmit a clock signal and data over a single line, perhaps using a self-clocking signal such as Manchester coding.

The design I'm working on has a number of chained units, with data fed into the first unit in the chain and passed along to subsequent devices. In order to make connection easy I'm using USB connectors, so I have four lines (VCC, GND, D+, D-) for communications. Ordinarily I'd just use one for clock and the other for data, but I'm concerned about data corruption and cross-talk over the distances involved (1ft or so). As such I'm planning on combining both signal and clock onto one line, then using LVDS for improved noise resistance - after all, USB is differential in the first place!

This would likely be trivial with a microcontroller, but I'm trying to avoid that for both complexity and cost reasons. Is there such a thing as a transceiver IC which translates between discrete clock and data pins and a combined self-clocking signal? What sort of keywords should I look for?

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  • \$\begingroup\$ Do you need to cascade the recovered clock, or are you regenerating the clock at each stage? \$\endgroup\$ – alex.forencich Jul 18 '17 at 14:35
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    \$\begingroup\$ What's the data rate? \$\endgroup\$ – The Photon Jul 18 '17 at 14:44
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    \$\begingroup\$ So each stage has a data in/clock in and data out/clock out? If each stage generates a clock with a 50% duty cycle and can tolerate an input clock with variable duty cycle, then it should be possible to build manchester encoders and decoders with discrete logic (XOR gate for encoder, XOR gate + flip-flop and fixed delay for decoder) \$\endgroup\$ – alex.forencich Jul 18 '17 at 14:55
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    \$\begingroup\$ Would not transmit clock & data separately on D+ and D- since those wires are twisted together and likely to cross-talk strongly (though with 1 ft at 500 kHz you could probably get away with it if you limit edge speed) \$\endgroup\$ – The Photon Jul 18 '17 at 15:06
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    \$\begingroup\$ Even recovering clock and data from a Manchester-encoded signal is going to require a few gates, a FF and some timing circuitry. A tiny (6/8/14-pin) microcontroller dedicated to this function would actually be physically smaller (fewer physical parts) and be more robust than something implemented with discrete gates or a PLD of some sort. Why exactly are you ruling it out? \$\endgroup\$ – Dave Tweed Jul 18 '17 at 15:25
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Self clocking serial protocols exist in a thousand variations everywhere magnetic recording to primitive ethernet communication, telephony to industrial and SCADA communication. These protocols and their designs have existed for over 40 yrs in my use as well as others.

There are many implementations depending on the bit rate, and expected BER, SNR.

The simplest encoders use 1T,2T transition intervals where 2T = is the 1/f, baud rate and have been defined as Bi-Phase or Manchester codes for Mark, Space and Invert define the toggle on centre bit transitions or Bi-Φ{M,S,I}. Early Hard Disk drives and present day Floppies conserved bandwidth using MFM which used 2T,3T. This expanded to Run-Length Limited (RLL) codes used in ethernet and many other serial comm. links which stretch the interval between clock transitions.

Once you choose a bit protocol, for clock and data sync, you must choose a frame sync, byte sync and bit orientation and message protocol , of which there are thousands , so why reinvent the wheel?

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Encoding uses the Clock and Data into an XOR gate for Mark (1) or Space (0) ( from early telegraph terms) to use a normal or inverted clock. Depending on the frame length and number of 0's, 1's or transitions, one chooses the best approach.

Simple Decoding uses a clock recover with a pulse edge created from every edge with XOR gate delay of <5%T and then a 1shot of 3/4T to sample the data value. Sophisticated Rx discriminators will integrate the entire bit energy over 1T interval.

Filtering is essential to avoid group delay in the signal band which causes bit shift and Intersymbol Interference. Critical Rx use Raised Cosine filter, while non-critical Rx use LPF 5xf approx. Differential signalling is better for CM noise immunity when signal are low compared to EMI.

There are many implementations freely available in HDL, AVR and programmable logic as well as discrete "old technology" one shots and XOR gates. Filters may be analog but some use more sophisticated digital filtering to minimize ISI and maximize SNR to get highest Bit Error Rate (BER), which as we know from Shannon's Law is directly related to SNR.

Volumes have been written on this subject decades ago , so it you seek, ye shall find.

Remote Controllers at low f use a pulse stretch or delay or duration modulation for 1's & 0's which compromises SNR/BER ratio but can work in a low noise environment.

Don't forget to include error detection, (Parity, or Hamming Code or CRC, or ECC ) and Clock loss of sync detect. Then you need frame sync detect, byte sync clock Error Detect logic etc.

Although not cheap or well stocked, this uses a 16x or 32x clock up to 1Mbps https://www.digikey.com/products/en/integrated-circuits-ics/specialized-ics/686?k=manchester&k=&pkeyword=manchester&v=20&FV=ffe002ae&mnonly=0&ColumnSort=0&page=1&quantity=0&ptm=0&fid=0&pageSize=25

> Is this to decode CANBUS ISO 11898 signals?

If so then look at SCAN921226H Receiver chip $10 with 8bit parallel out and timing signals.

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  • \$\begingroup\$ This is not for CANBUS and I think I'm ultimately going to have to abandon this approach; the complexity of the decode makes things less feasible. I was hoping for a drop-in transceiver part but it seems that such a part does not exist. \$\endgroup\$ – Polynomial Jul 19 '17 at 9:11
  • \$\begingroup\$ The flow of information and cost is not well defined in your question, making it too myopic and off track like an XY question. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jul 19 '17 at 16:31
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You want a 'serializer' and a 'deserializer'. Note that for LVDS, it's probably not going to come out bit-serial. More likely it will be a parallel interface of 8 or 16 bits. Note that you may have trouble finding one slow enough for your application.

First google result for 'lvds serializer' is ds92lv16. That part has a serializer and a deserializer in one package with two 16 bit parallel interfaces. Note that the minimum clock speed is 25 MHz, corresponding to 400 Mbps.

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  • \$\begingroup\$ If the data is already available in serial, like OP seems to imply in the question, then no serializer/deserializer is needed. Manchester encoding & decoding can be done with a few gates. \$\endgroup\$ – The Photon Jul 18 '17 at 14:21
  • \$\begingroup\$ Yes, the data is already serial. It's a similar kind of intended communications model to how WS2812 LEDs pass data. From what I understand, LVDS transceivers operate with bit-level granularity as they're essentially stateless. \$\endgroup\$ – Polynomial Jul 18 '17 at 14:23
  • \$\begingroup\$ @Polynomial, LVDS transceivers are just Low-Voltage Differential Signaling drivers, they operate on any digital signal that is fed to them. There is no "bit-level granularity" nor any inherent states. You must be confusing the term with some more complex logical blocks (like SERDES or else) that USES LVDS signaling levels as input-output. \$\endgroup\$ – Ale..chenski Jul 18 '17 at 17:12
  • \$\begingroup\$ @AliChen That's basically what I said, yes. I'm not sure that any terminology distinction matters here - I'm using a TI DS90LV019 for LVDS and it does exactly what I need in that regard (simple in/out) \$\endgroup\$ – Polynomial Jul 19 '17 at 9:09
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Evaluate Pulse Duration Modulation. With a rising edge to launch each bit, trigger a one-shot to timeout at 50% and clock the data into FF. Make the bit-duration either 33% or 63%, trivially.

Or 25% and 75%, for more noise immunity.

Avoid durations close to 100%, because the buss (your 2 wires) needs time to reset back to zero.

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    \$\begingroup\$ The really easy bit is the transmit side and the definitely harder part is the receive side and you haven't covered that. \$\endgroup\$ – Andy aka Jul 18 '17 at 16:52
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It looks like the task is in well-known area of industrial automation. I am afraid the challenge is not only how to make a self-clocking data, but many other issues can arise, arbitration, address decoding, etc. So you would need to partition the protocol into packets and messages, etc. One of the solutions to the problem of communication between distributed objects and sensors is called "CAN bus".

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