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I'm interested in the history of the logic design for the edge-triggered D flip-flop, as used in the SN7474. The design is composed of three set-reset latches (six NAND gates total) per flip-flop.

Does anyone know what year the SN7474 was introduced, or have an early datasheet for it (prior to the 1973 TTL Data Book For Design Engineers 1st Edition)? I've found it listed in distributor catalogs as far back as 1967 (year edited on 2017-07-21, previously I wrote 1971).

Another early datasheet I've found using this specific logic design for an edge-triggered D flip-flop is from a non-7400-series TTL chip, the Motorola MC3060/3160, which is a member of the MTTL III MC3000/MC3100 series.The MC3060 is covered in the Motorola 1968 IC databook, on page 4-138. The 1976 TI TTL Data Book For Design Engineers 2nd Ed. lists the SN74H74 as direct replacement for the MC3060.

I've searched US patents for edge-triggered flip-flop design, but have not found one specifically for the three S-R latch design.

The subject came up as a result of a discussion on a private mailing list regarding the fact that the conventional J-K master-slave flip-flop design is NOT edge-triggered; pulses on J and/or K while the clock is high but stable can affect the Q (and not-Q) outputs of the FF at the following falling edge of the clock. That behavior is known as "pulse catching", and such a flip-flop is properly called pulse-triggered or level-triggered, but not edge-triggered. Early datasheets on J-K master-slave flip-flops actually had correct terminology and specifically stated that J and K should not change while the clock is high.

There are true edge-triggered J-K flip-flops which use a derivative of the three-S-R-latch D FF design, effectively generating an internal D input to the FF from J, K, and Q (and/or not-Q). The 74x109 is an example of that, using a not-K input rather than true K.

Master-slave D flip-flops effectively are edge triggered, unlike J-K master-slave. It is possible to build a true edge-triggered J-K master-slave flip-flop, by using a D master-slave with the internally generated D as described above.

CMOS edge-triggered flip-flop designs are almost always based on a master-slave design using transmission gates.

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    \$\begingroup\$ I know for sure that the Eniac was using SR latches in its accumulator program control unit using 6SN7's. Must be an edge triggered D flop in there somewhere. Are you including tubes? Or strictly limited to just semiconductor devices in this history thing? (And I may have some SN7474 parts from 1972, still. I know I had them before I was able to get the fancy databook -- which I was later very happy to get. My memory is vague, but I might have paid $5 back then for it. I remember getting it very well, though.) \$\endgroup\$
    – jonk
    Commented Jul 20, 2017 at 0:36
  • \$\begingroup\$ Tube-based SR latches (bistable latches or bistable multivibrators, though not usually called that at the time) existed in the 1940s. AFAIK, there were never any edge-triggered flip-flops of the modern (1970s IC) style used in tube equipment, or even discrete-transistor equipment, because that would be a huge waste of resources. Tube FFs were often edge-triggered by virtue of a capacitively-coupled input, which was also sometimes used with discrete-transistor and even with early IC designs. \$\endgroup\$
    – Eric Smith
    Commented Jul 20, 2017 at 2:08
  • \$\begingroup\$ Thanks Eric for the correction on the narrow point you are making. I am gathering your question barely scratches the surface and I'll be very interested in a paper on the topic you might write when all is said and done. \$\endgroup\$
    – jonk
    Commented Jul 20, 2017 at 2:47
  • \$\begingroup\$ I don't anticipate writing a paper on it, however, if I obtain information from sources outside this forum, I'll post it here. I suppose it's not surprising that it's hard to find this kind of historical information given that everyone is normally focused on the latest and greatest parts. (Myself included.) Aside from asking here and in other online forums, I will spend some time at the Colorado School of Mines library perusing 1960s electronics journals. \$\endgroup\$
    – Eric Smith
    Commented Jul 20, 2017 at 2:52
  • \$\begingroup\$ I think your effort (and the insights developed through that process) are worthwhile and should be captured for the benefit of others, if possible. But of course only if you feel able to afford that final step. \$\endgroup\$
    – jonk
    Commented Jul 20, 2017 at 3:04

2 Answers 2

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The Block II Apollo Guidance Computer (1965) used the three-SR edge-triggered flip flop circuit. I don't know if this was the origin of the circuit, but this pushes the date back a few years. The circuit is similar to the 7474's flip flop, but using NOR gates instead of NAND gates.

The AGC was one of the first IC-based computers, built out of NOR gates. It used S-R latches extensively; the edge-triggered flip flop is not as common but used for example here and here. A seven-gate variant is here.

(Thanks to Mike Stewart for info.)

Schematic of an edge-triggered flip flop built from 6 NOR gates.

Edit: I've come across a 1966 document calling this a "Westinghouse flip flop" (Apollo Block II and LEM Computer Design Review page E-1). American Microelectronics Data 1964-1965 shows the Westinghouse WM-2203 "six-gate binary counter" using this circuit. There's also a Westinghouse patent 3018388A for a flip flop that might be related. Finally, this NASA document from 1966 describes Westinghouse building a power supply synchronizer IC using this flip flop circuit, called a "six gate binary". I conclude that Westinghouse had a key role in the creation of this flip flop.

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    \$\begingroup\$ As drawn, it's an edge-triggered T flip-flop, but it's clearly very similar to the edge-triggered D FF design. For a D FF, 37224 pin E would be the FF's D input (instead of being connected to 37726 pin K), and 37721 pin B would be connected to 37224 pin K. I wonder whether the Instrumentation Laboratory has any engineering notebooks documenting the design process. \$\endgroup\$
    – Eric Smith
    Commented Aug 8, 2019 at 22:29
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Read the RTL book by Don Lancaster in 1968. Its on http://www.archive.org

RTL came before TTL and around p 112 he describes FF's in detail, but not a component databook.

but if you search there, you will find all the databooks too.

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  • \$\begingroup\$ That www site doesn't work for me. Just FYI. \$\endgroup\$
    – jonk
    Commented Jul 20, 2017 at 0:28
  • \$\begingroup\$ fixed oops......... archive.org/details/RTL_Resistor-Transistor_Logic_Cookbook \$\endgroup\$
    – D.A.S.
    Commented Jul 20, 2017 at 0:33
  • \$\begingroup\$ Thanks. What? The wayback machine? I only use that to find old, no longer functioning web links. Plugged in don lancaster rtl and could not find it. Are you able to do so? If so, I'd appreciate a more complete link. \$\endgroup\$
    – jonk
    Commented Jul 20, 2017 at 0:36
  • \$\begingroup\$ I've read that, and databooks covering RTL, and as far as I can tell, there were no true edge-triggered D flip-flops, let alone of the three-SR-latch design. I haven't found any in DTL or ECL either. \$\endgroup\$
    – Eric Smith
    Commented Jul 20, 2017 at 2:11
  • \$\begingroup\$ I'm tentatively going to have to retract my previous comment. It looks like the MC778/878 (mW RTL) does use the three-S-R-latch design and is edge-triggered. It's described in Lancaster's RTL Cookbook starting on page 128, but he doesn't really call attention to it being truly edge triggered. It appears in the 1968 Motorola IC databook, but without full data, which is present in the 1968 databook. It's cruder than the MC3060 and SN7474, in that the async preset and clear only work when clock is high. It's not clear that it predates the MC3060. \$\endgroup\$
    – Eric Smith
    Commented Jul 20, 2017 at 2:48

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