Comparator Output Unstable

Question

I have designed a comparator with hysteresis using LT1719. When I apply no signal, at op_amp_2, I expect the output to be high. However I see a sine wave at the output. This is the schematic of the circuit:

This is snapshot of the PCB layout:

I initially thought that since the DC levels at + and - are very near, this could cause oscillation when there is no signal, so I changed R19 to 10 Kohm. At first it worked as expected (output high 4.8V) then I applied a signal (at op_amp_2) and on removal of signal, the output started oscillating.

Could anyone suggest how I can fix this?

Answer 1

You have a positive-feedback oscillator, because the +Vin (pin2) is routed directly under the Vout (pin7).

EDIT Also, the Rfeedback 604Kohm drives 5pf or more, what with 3 causes of capacity on Vin+ :::

1) the input capacity of the comparator

2) the side capacitance of that long Vin+ trace to the surround GND

3) the many bits of metal over that long Vin+ trace

EDIT The 604kohm is too large to quickly implement 15Kohm/600Kohm * 5v = 150 millivolt of hysteresis. Reduce your resistors on Vin+ by 10X, to 1.87K, 10.7K, 60.4K

Assume you have 2mm by 4mm area of coupling between pin7 and pin2, on pin7 side of the IC. With PCB thickness of 1/16". What is the capacity?

C = Eo * Er * area/distance = [9e-12Farad/meter * 5 * 4mm * 2mm / 1.5mm] * meter/1000mm

C = 9e-12 * 5 * 6/1.5 * 1/1000 = 180e-12-3 = 180e-15 = 0.18pF

Assume Cnode(pin2) is 3.6pF. The 5 volts output swing is attenuated by 0.18/3.6 or 1/20 thus V_injected_pin2 of 5/20 = 0.25 volts.

Place a scope probe on Pin2, and see that 0.25 volts (but will be further attenuated by 10pF or 15pF of the scope probe, to approximately 50 milliVolts).

---

The timeconstant on Vin+ is 0.18pF * 15Kohm or 3nanosecond feedback thru the parasitic cap I computed. There is also parasitic across the feedback R (604Kohm).

Cure? solder-tack a 10pF across the 604Kohm Rfeedback, to ensure the hysteresis is LARGE, and slowly decays. Use a 10pF leaded, to make it easy.

Answer 2

These devices are really fast, and your impedances at the input pins are in the 10K range. Only a little parasitic capacitance will cause oscillations. When you remove the signal, tie the input to ground near the part. This is one way to lower the impedance on the minus input. You will have to also lower the impedance on the plus input by either adding capacitance or lowering the resistance. If you need the fast response, try for matched input impedance on the inputs with a value around a few hundred ohms or less. Your layout looks good. If you don't need single-digit nanosecond response, you could also try a more mundane comparator.

To get the impedance down, try adding a resistor between point op_amp_2 and ground near the comparator of 499 ohms (your input op amp will have to drive this load; if it can't, keep the resistance as low as you can.) This will probably keep you from oscillating when you remove the input. Then change R6 to 499 and adjust R21 and R5 to keep the same ratio.

Answer 3

With parasitic LC, the schematic does not resemble the layout and your source and load impedances are mismatched and unlike better ECL comparators you are not operating in current mode, and with high impedance it is very sensitive to stray coupling. Your signal is also unbalanced and source impedance is undefined except 10k when disconnected and low when connected thus ground noise is critical with low hysteresis and it appears your noise coupling exceeds your ~5% hysteresis.

With 5ns prop delay in spec and half that for small swings, I would expect 20Mhz and your 10:1 probe probably also resonates at 20MHz with a 4" ground clip.

In effect you have a Relaxation Oscillator like a CMOS Schmitt inverter with R feedback and small C input to ground.

It appears you ignored the advice in the datasheet.

High Speed Design Considerations

Application of high speed comparators is often plagued by oscillations. The LT1719 has 4mV of internal hysteresis, which will prevent oscillations as long as parasitic output to input feedback is kept below 4mV. However, with the 2V/ns slew rate of the LT1719 outputs, a 4mV step can be created at a 100Ω input source with only 0.02pF of output to input coupling. The LT1719’s pinout has been arranged to minimize problems by placing the sensitive inputs away from the outputs, shielded by the power rails. The input and output traces of the circuit board should also be separated, and the requisite level of isolation is readily achieved if a topside ground plane runs between the output and the inputs. For multilayer boards where the ground plane is internal, a topside ground or supply trace should be run between the inputs and the output.

specs

It depends what you you want to do with your input signal thru the comparator in terms of dynamic range and bandwidth of signal and Noise, impedance range of source signal and noise on cable incl. gnd noise, asymmetry of output, prop delay. Until you define these or at least understand them a great design cannot be achieved.

I agree with @analogsystemrf for now a bandaid fix is to add more hysteresis with 10pF using 603 cap over R21.

Next layout consider my specs and the datasheet examples for 50 ~200 Ohm high speed comparators.

Answer 4

Layout is contributing part of the problem. Your circuit impedances are large, which means little energy is required to impose a signal. Can you scale your impedances down?