I was trying to solve the below question.
A long wire may be considered as a series of RC element where R is the serial resistance and C is the ground capacitance. In figure 1, there is no intermediate gate after first Driver (between a and b). In figure 2, there are 2 Gates in the circuit with Gate_Delay = RC. If delay between a and b for figure 1 is x and for figure 2 is y, what’s the correct relationship between x and y.
I think y is less than x because as length of interconnects increases delay increases. But I am not able to comment on figure 2. What is the delay in the ckt of figure 2?