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I am designing a H bridge converter which is supplied with a 400VDC bus.

The switching frequency will be 20kHz

I want fit an LC filter to the output so that a sinusoidal voltage is produced, the operation and design of the filter is something that I have a good understanding of

My question relates to the capacitor type and dv/dt ratings

I thought metallised polypropylene capacitors were a good choice for an inverter filter capacitor and I have used them in the past with relatively low DC bus voltages (circa 24VDC)

A 400VDC bus isn't something I have much experience with my plan was to use a 680uH inductor like a Bourns 2322-RC and a 10uF capacitor like a Kemet R463W510050M1K. The cutoff frequency would be around the 2kHz mark

http://uk.rs-online.com/web/p/polypropylene-film-capacitors/8752308/

However the datasheet tells me the max dv/dt is 100V/us, my H bridge will use IGBT's so the turn on time will be quite fast lets assume it switches on in 0.1us

400V in 0.1us is a serious amount of dv/dt and the capacitor is going to be very stressed and fail in no time at all

Can anyone advise me on what the best course of action is to protect the capacitor?, I have seen commercial drives use these types of capacitors so I am wondering how they are designed to last

Do we add a resistor in series with the capacitor to slow the rise times or fit in a dv/dt filter before the output capacitor so that it absorbs the bulk of the dv/dt stresses?, I believe a MLCC capacitor would be a good choice for this but I am open to ideas and keen to understand how to make a robust design

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    \$\begingroup\$ Not sure if your capacitor will see such stress, since you will put a choke (or maybe more of them) at the output, first. \$\endgroup\$ – Marko Buršič Jul 23 '17 at 14:51
  • \$\begingroup\$ Schematic please. \$\endgroup\$ – winny Jul 23 '17 at 21:52
  • \$\begingroup\$ Schematic from the PCB software isnt complete yet (I havent decided which cap yet), my Matlab sim shows the planned layout though \$\endgroup\$ – Jamie Lamb Jul 23 '17 at 22:13
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Can anyone advise me on what the best course of action is to protect the capacitor?, I have seen commercial drives use these types of capacitors so I am wondering how they are designed to last

The capacitor is after the inductor so the rise time of the voltage on the capacitor will be substantially slower than 0.1 us. This problem is ideally suited to something like LTSpice and would show you precise results very quickly and easily.

However, if you want a broad-brush estimation of the worst case dv/dt then think about the inductor being fed with a step of 400 volts and ask yourself what the current ramp would look like. For instance V = L di/dt so, 400 volts and 680 uH gives a current rate of change of 588 amps per millisecond.

This in turn can be assumed to flow into the capacitor and knowing I = C.dv/dt you can do a little algebra/calculus to show what dv/dt is for the capacitor. Or just trial some numbers - the first PWM pulse at 20 kHz could be assumed to be wide i.e. occupy the full 5 us of the period so the current will rise to about 3 amps and this will give rise to a dv/dt of 3/10 uF = 0.3 volts per microsecond.

It looks to me like you are well inside the dv/dt limit for your chosen capacitor but, I would just go straight to LTSpice (or your favourite sim) for confirmation.

I'm also wondering why you have chosen 2 kHz to be the resonant frequency of the invertor's filter and not something a bit lower. For instance if your inverter is generating 50 Hz, then a more feasible low pass filter would have a resonance that is logarithmically half way between 50 Hz and 20 kHz i.e. 1 kHz.

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  • \$\begingroup\$ I have some Matlab/Simulink simulations of drives and LC filters, they use ideal components so I will try and adapt them perhaps using powersim. I dont know much about spice unfortunately I could never get away with it. I didnt think an inductor would do much to limit the rise time of a voltage just affect a current with the old Ldi/dt. The filter cut off isnt set in stone just real world components limit me its hard to find a cap above 10uF with a decent dv/dt and an inductor for 2A starts getting enormous. \$\endgroup\$ – Jamie Lamb Jul 23 '17 at 12:42
  • \$\begingroup\$ It was my understanding that if the cut off is ten times less than the switching frequency and ten times greater than the fundamental then its good to avoid resonance so thats a cut off between 1kHz and 2kHz with me just inside the safe band \$\endgroup\$ – Jamie Lamb Jul 23 '17 at 12:42
  • \$\begingroup\$ you are right an inductor won't do much to limit the risetime of voltage, just current. HOWEVER... the capacitor's risetime is related to its charging current. if the current is limited, the voltage risetime will be \$\endgroup\$ – JonRB Jul 23 '17 at 12:53
  • \$\begingroup\$ Yes yes of course, the current spikes into the capacitor will be smoothed by the inductor according to Ldi/dt. isnt this site great just typing out your question maks you think it through thoroughly and then all the brains come together and I just love it. Thanks for teaching me the fundamentals =-) \$\endgroup\$ – Jamie Lamb Jul 23 '17 at 13:06
  • \$\begingroup\$ See my rough calculation added into my answer. I think you are easily inside the dv by dt limit. \$\endgroup\$ – Andy aka Jul 23 '17 at 13:12
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You have several filter options:

schematic

simulate this circuit – Schematic created using CircuitLab

1 is the simplest, however the wire on the right side of the load will carry fast switching transients and behave like an antenna.

2 somehow fixes this problem by adding another inductor, but to reduce elecreomagnetic emissions, we'd really need caps to ground, not across the load.

3 tackles this: C1 and C2, together with the inductors, filter the sharp switching edges, and emissions are controlled. However, we need two big inductors, and two big caps.

4 saves some money on capacitors. C5 and C6 have smaller values, and only get rid of high speed switching transients, while C4 actually smoothes the output waveform.

5 saves more money on the inductors. L9/L10, C9/C10 have small values are only there for EMI filtering. At their output, you still got square waves, but with nice slow edges so your wires don't act as antennas. These components are smaller and cheaper. Then you only need one large L and C (L11 and C6) to actually smooth out the waveform into a sine.

Note that high value, physically large caps and inductors have lots of parasitics (inductors have interwinding capacitance, and caps have series inductance) which means they will suck at high frequencies. Smaller components (with less parasitics) filter out your EMI much better. Thus, this scheme is likely to be the best wrt. emissions.

EDIT:

You can guesstimate the ESL (series inductance) of a cap. The green stuff is your PCB, and the red line is the current's path. It makes a square loop (depending on your layout also). So you can use a "square loop inductance" calculator. Physically larger caps have more loop area, thus more inductance. Putting a much smaller cap in parallel lowers inductance, thus improves EMI filtering. Same with fat wide tracks, planes, etc.

enter image description here

Once you have your guesstimated value, you can simulate the result.

Several caps in parallel have lower inductance too.

Same thing for inductor interwinding capacitance. Big inductors have a lot of parasitic cap. A good trick is to put a much lower value inductor in series, preferably a 1-turn one (ie, slip a ferrite bead core onto the wire).

EDIT: Thanks to Teodor for refreshing my memory on these things.

Here's an example where the left side of the h-bridge switches once per period, and the right side does all the fast stuff. Switching losses are minimized. Filter on left side can be a simple anti-EMI LC filter with very low values. However the signal's common mode flips every half period (not shown on graph). If this is not a problem, then this is the best solution.

Make sure the LC circuits are properly damped. You'll need to add some zobels, or use caps with the right amount of ESR.

Also here, the large filter cap has to be across the load. The left halfbridge flips voltage every half period, and the right one adjusts its PWM accordingly, but since I took the opportunity to skip the large LC on the left side, during sign transition both halves do not behave equal, which creates a spike if the filter cap goes to GND. I used behavioral voltage sources to switch the FETs. Try it in your favorite simulator ;)

enter image description here

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  • \$\begingroup\$ Allow me to digest this great reply, 3 was the original plan \$\endgroup\$ – Jamie Lamb Jul 23 '17 at 13:07
  • \$\begingroup\$ OK! As for your caps, if you need 10µF 600V, you can build it with smaller caps in parallel. Maybe it will be cheaper or easier to source, you should compare prices. But smaller caps have lower inductance (see edit). \$\endgroup\$ – peufeu Jul 23 '17 at 13:19
  • \$\begingroup\$ @JamieLamb You did not mentioned your inverter driving method. The most common driving method for sine wave inverter switches one half of the bridge at low frequency 50/60Hz and the other half at high frequency with sine modulated PWM. If this is the case filters 3,4,5 will produce more stress on some of the filtering capacitors. I would use filter 1 or 2. \$\endgroup\$ – Todor Simeonov Jul 23 '17 at 20:12
  • \$\begingroup\$ The inverter will be driven with sine reference PWM on both phases with 180 degree phase shift so I achieve a peak of 400V. Filter three looks similar to filter 2 but we save a capacitor and I imagine it works very similar as one side is effectively grounded the extra series inductor will help though \$\endgroup\$ – Jamie Lamb Jul 23 '17 at 20:20
  • \$\begingroup\$ I would love to know how to calculate the dv/dt, worst case theoretical whatever will do I have tried hard! \$\endgroup\$ – Jamie Lamb Jul 23 '17 at 20:23
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I threw together a Matlab simulation

H bridge outputs

Theres an H bridge with a 400VDC bus supplying an RLC filter (unloaded)

R = 0.1, L = 680u and C = 10u

the Va-Vb is a sine wave with a 400V peak as expected, the Current peaks at around 8A

I measure the voltage across the capacitor and differentiate it, the dv/dt max is only 0.8, does this look right?, is that 0.8V/s?? enter image description here

Andy I am interested in your rough calculation

I understand with a step input the drop over the inductor is the full 400V (instant risetime)

V/L = di/dt

di/dt = 588235

I also understand that Ic = Cdv/dt

Considering the absolute worst case of driving current into the C for an entire 50us (20kHz period)

then Ipeak is 0.00005*588235

I peak is 29.4A so by my calculations

dv/dt = 29.4/(10/10^6)

dv/dt = 2.94MV/second

dv/dt = 0.294V/us

Is this correct?, its very different to the dv/dt = 0.8 that the simulation tells me, just need to wrap my head around the numbers

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