The question is is it going to be any better?
It sounds to me like it will be a bit better in that it will reduce the error between the two clocks - the capacitors do that - they trim the phase response of the filter formed around the crystal, the output impedance of the silicon and the capacitor at the output. I'm thinking Pierce oscillator topologies here like this: -
But it quite equally applies to other crystal oscillator topologies.
C1 and R1 add a bit of extra phase shift that is needed to make the circuit oscillate because, without them being present, a perfect inverting gate can't be encouraged to produce the extra few degrees and it won't oscillate. This happens now and then and the linked question below is related.
Of course, even without R1 as an actual component, the internal output impedance of the gate serves as R1. Note that for the pierce oscillator R might be internal to the "chip" or actually present on the circuit board.
It turned out that it's completely missing any capacitors on crystal
There will always be capacitance on a gate's input so that accounts for maybe 5 pF and a slight delay in the inverter (just a few nano seconds) can bring about the extra phase change needed to make the circuit oscillate. However, some circuits without output capacitance will never oscillate.
What are consequences of soldering different capacitors to the quartz
Different capacitances was demonstrated to you when no actual capacitors were fitted. The input capacitor might have been 5 pF and the delay of the inverting gate brings about the extra phase change needed to make the oscillator oscillate. It is a bit hit and miss like this but can work.
Here's a picture of a sim I did some time ago that shows the bode plot of a 10 MHz crystal and two capacitors. The capacitors on the input and the output of the gate were varied simultaneously as shown. The whole X-axis covered about 100 kHz so it puts it into context how little you can shift a crystal oscillator in reality: -
If I varied the capacitor between 20 pF and 10 pF you can see the frequency range where the transfer function passes through 180 degrees. A little below 10 pF there is a point where the phase shift never reaches 180 degrees and the only way the circuit will oscillate is with the inverting gate running with enough extra phase shift over and above the 180 degrees it is expected to deliver.
The circuit will fail to oscillate if the inverter has to run at a frequency above the anti resonant node in order to produce the required extra phase shift.
Above picture taken from my answer here.
Here's a brand new plot of the phase shift when only the output capacitor is varied (the output capacitor being the one normally associated with the inverter output): -
It will oscillate with 20 pF, 10 pF and just about oscillate with close to 5 pF but any lower and it won't oscillate theoretically.