I'm building my own regulated linear DC power supply based on the Farnell L30 (service manual and circuit diagram here) and I'm sticking mainly to the original design with some modifications for parts and improvements.
The section of interest for this problem is shown below:
For completeness, I'm using some nice old 2.5k pots (course and fine) and I'm driving the Howland current source (via the pots) with a steady, TL431 based 5V supply. Also, instead of 15V and -5V rails, I have +/-12V rails.
I haven't included a schematic of these changes because they aren't relevant to this issue, as I'll explain shortly.
The problem I'm having is that the voltage output is very non-linear as I adjust the pots. Ignoring the fine adjustment (set to 0), if I divide the course pot adjustment into 9 segments, roughly half the 30V output is delivered in the first 2 segments, with the remainder forming a linear ramp to 30V.
Here's a plot of what I'm talking about:
It took quite a bit of debugging, but I've concluded that the issue lies with the voltage comparator op amp (IC2 in the schematic). In my circuit, this is a FET input TL082 and it seems this has something to do with bias currents.
When I had the 10k resistors at the inputs, I got the plot above. If I change R14 to 20k, I get the following plot:
Not exactly linear, but the rate of change at the start is less.
It's extremely difficult to debug this issue properly because any attempt to measure voltages at the op amp inputs causes the op amp to rail with the loss of control causing the pass transistors to saturate (not desirable). Obviously, the voltmeter draws current and this will affect the reading and I need the control loop in place to make effective measurements - so a bit of a pain really.
However, I can conform the following:
The pots are linear
The current source is linear (to test this I tied the current source to the 0V reference rail through a 1k resistor and tracked the changes - all perfect)
The supply rails to the control section and the 5V current source driving voltage are all steady.
So, after all that, would you agree that this may be the cause of the issue I'm seeing (I have experimental evidence, but I still don't grasp the theory)?
Can somebody provide a good theoretical explanation as to the effect I'm seeing?
Some pictures to give you an idea of the layout:
Looks like @PlasmaHH was on the money. I have quite a bit of oscillation at the voltage comparator and the output. Below I've included some pictures (excuse the poor image quality!). At 5V (as read erroneously from my DMM at a DC setting) the oscillation frequency is about 142 kHz and I have a 1V pp oscillation at the inverting pin of the voltage comparator op amp (image#1) and a staggering 36V pp at the supply output (image#2).
Looks like I'll need to sort out these oscillations before going any further. Any ideas about which components to tweak to kill these?